公开(公告)号：US20240330201A1

公开(公告)日：2024-10-03

申请号：US18534532

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Alan Gara ,  Robert Wisniewski ,  Douglas Joseph ,  Samantika Sury ,  Jai Dayal ,  Rolf Riesen

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: A system and method for address translation in a multi-node computing system. In some embodiments, the system includes a first node. The first node may include: a core; and a global address translation circuit, the core including: a core processing circuit; and a memory management unit configured to map local virtual addresses to global virtual addresses, the global address translation circuit being configured to map global virtual addresses to global physical addresses.

公开(公告)号：US20240330188A1

公开(公告)日：2024-10-03

申请号：US18491183

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jai Dayal ,  Douglas Joseph ,  Samantika Sury

IPC: G06F12/084 ,  G06F9/54

CPC classification number: G06F12/084 ,  G06F9/544

Abstract: Provided is a method for data processing, the method including generating, by a host, a work request in a queue in a shared memory, reading, by an accelerator circuit, the work request from the queue in the shared memory, the shared memory being a physical memory that is common to the host and the accelerator circuit, and performing, by the accelerator circuit, an operation on data in the shared memory based on the work request.