公开(公告)号：US09312188B2

公开(公告)日：2016-04-12

申请号：US14169608

申请日：2014-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

IPC: H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract translation: 在制造半导体器件的方法中，第一栅电极和第二栅电极分别设置在衬底上，第一栅极电极和第二栅电极分别形成在衬底的第一区域和第二区域中。 导电缓冲层沿着第一栅电极和第二栅电极的侧壁以及第一栅电极和第二栅电极的上表面形成。 形成覆盖缓冲层上的基板的第一区域的第一掩模图案。 使用第一掩模图案作为离子注入工艺的掩模，在第二栅电极的侧面的衬底中形成第一杂质区。