公开(公告)号：US09123655B2

公开(公告)日：2015-09-01

申请号：US14190797

申请日：2014-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hwan Oh ,  Yu-Ra Kim ,  Tae-Sun Kim ,  Kwang-Sub Yoon

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3086 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139

Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.

Abstract translation: 一种制造半导体器件的层图案的方法，所述方法包括在蚀刻对象层上形成抗反射涂层（ARC）层，使得ARC层包括具有酰亚胺基团的聚合物; 在ARC层上形成光刻胶图案; 通过光致抗蚀剂图案曝光的ARC层的湿蚀刻部分以形成ARC层图案; 并使用光致抗蚀剂图案蚀刻蚀刻对象层作为蚀刻掩模以形成层图案。

公开(公告)号：US09373698B2

公开(公告)日：2016-06-21

申请号：US14505662

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Sun Kim ,  Jae-Kyung Seo ,  Ji-Ho Kim ,  Kwang-Sub Yoon ,  Bum-Joon Youn ,  Ki-Man Lee

IPC: H01L23/52 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/027 ,  H01L29/51

CPC classification number: H01L29/66636 ,  H01L21/0276 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/165 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7834

Abstract: In a method of manufacturing a semiconductor device, an isolation layer pattern is formed on a substrate to define a field region covered by the isolation layer pattern and first and second active regions that is not covered by the isolation layer pattern and protrudes from the isolation layer pattern. A first anti-reflective layer is formed on the isolation layer pattern. A first photoresist layer is formed on the first and second active regions of the substrate and the first anti-reflective layer. The first photoresist layer is partially etched to form a first photoresist pattern covering the first active region. Impurities are implanted into the second active region to form a first impurity region.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成隔离层图案，以限定由隔离层图案覆盖的场区域和未被隔离层图案覆盖并从隔离层突出的第一和第二有源区域 模式。 第一抗反射层形成在隔离层图案上。 在基板的第一和第二有源区域和第一抗反射层上形成第一光致抗蚀剂层。 部分蚀刻第一光致抗蚀剂层以形成覆盖第一有源区的第一光致抗蚀剂图案。 将杂质注入到第二有源区中以形成第一杂质区。

公开(公告)号：US09312188B2

公开(公告)日：2016-04-12

申请号：US14169608

申请日：2014-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

IPC: H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract translation: 在制造半导体器件的方法中，第一栅电极和第二栅电极分别设置在衬底上，第一栅极电极和第二栅电极分别形成在衬底的第一区域和第二区域中。 导电缓冲层沿着第一栅电极和第二栅电极的侧壁以及第一栅电极和第二栅电极的上表面形成。 形成覆盖缓冲层上的基板的第一区域的第一掩模图案。 使用第一掩模图案作为离子注入工艺的掩模，在第二栅电极的侧面的衬底中形成第一杂质区。