公开(公告)号：US09646967B2

公开(公告)日：2017-05-09

申请号：US14990951

申请日：2016-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Kim

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966

Abstract: Semiconductor devices are provided. The semiconductor device includes a first fin portion and a second fin portion arranged on a substrate and extended in a first direction, the first fin portion and the second fin portion being spaced apart from each other in the first direction, a field insulating layer between the first fin portion and the second fin portion and having an upper surface thereof lower than an upper surface of the first fin portion, a first metal gate extended in a second direction on the first fin portion and a silicon gate extended in the second direction on the field insulating layer and contacting the field insulating layer.

公开(公告)号：US09502417B2

公开(公告)日：2016-11-22

申请号：US15046572

申请日：2016-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/165 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract translation: 半导体器件包括：衬底，包括第一有源区，第二有源区和第一有源区和第二有源区之间的场区;以及栅极结构，形成在衬底上以跨过第一有源区，第二有源区和场 地区。 栅极结构包括彼此直接接触的p型金属栅电极和n型金属栅极电极，p型金属栅极电极从第一有源区域延伸到第二有源区域的一半以下。

公开(公告)号：US09502416B1

公开(公告)日：2016-11-22

申请号：US14990992

申请日：2016-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Kim

IPC: H01L27/092 ,  H01L29/49 ,  H01L27/108 ,  H01L27/11 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/1116 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes first through fourth areas, first through fourth gate stacks, the first gate stack includes a first high-dielectric layer, a first TiN layer to contact the first high-dielectric layer, and a first gate metal on the first TiN layer, the second gate stack includes a second high-dielectric layer, a second TiN layer to contact the second high-dielectric layer, and a second gate metal on the second TiN layer, the third gate stack includes a third high-dielectric layer, a third TiN layer to contact the third high-dielectric layer, and a third gate metal on the third TiN layer, and the fourth gate stack includes a fourth high-dielectric layer, a fourth TiN layer to contact the fourth high-dielectric layer, and a fourth gate metal on the fourth TiN layer, the first through fourth thicknesses of the TiN layers being different.

Abstract translation: 半导体器件包括第一至第四区域，第一至第四栅极堆叠，第一栅极堆叠包括第一高电介质层，与第一高电介质层接触的第一TiN层和第一TiN层上的第一栅极金属 所述第二栅叠层包括第二高电介质层，与所述第二高电介质层接触的第二TiN层和所述第二TiN层上的第二栅极金属，所述第三栅叠层包括第三高电介质层， 第三TiN层与第三高电介质层接触，第三栅极金属在第三TiN层上，第四栅叠层包括第四高电介质层，与第四高电介质层接触的第四TiN层，以及 在第四TiN层上的第四栅极金属，TiN层的第一至第四厚度不同。

公开(公告)号：US09312188B2

公开(公告)日：2016-04-12

申请号：US14169608

申请日：2014-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Sang-Duk Park ,  Jae-Kyung Seo ,  Kwang-Sub Yoon ,  In-Gu Yoon

IPC: H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545

Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.

Abstract translation: 在制造半导体器件的方法中，第一栅电极和第二栅电极分别设置在衬底上，第一栅极电极和第二栅电极分别形成在衬底的第一区域和第二区域中。 导电缓冲层沿着第一栅电极和第二栅电极的侧壁以及第一栅电极和第二栅电极的上表面形成。 形成覆盖缓冲层上的基板的第一区域的第一掩模图案。 使用第一掩模图案作为离子注入工艺的掩模，在第二栅电极的侧面的衬底中形成第一杂质区。

公开(公告)号：US09305922B2

公开(公告)日：2016-04-05

申请号：US14633280

申请日：2015-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Youn Kim

IPC: H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/4966

Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.

公开(公告)号：US09048236B2

公开(公告)日：2015-06-02

申请号：US13947411

申请日：2013-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Jong-Mil Youn ,  Jong-Joon Park ,  Kwang-Yong Jang ,  Jun-Sun Hwang

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/518 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench.

Abstract translation: 半导体器件包括形成在衬底上的层间绝缘膜，所述绝缘层包括沟槽。 在沟槽的底面上形成栅极绝缘层，在沟槽的底面上的栅极绝缘层上形成反应防止层。 在沟槽的反应防止层上形成替代金属栅极结构以填充沟槽。

公开(公告)号：US20140103441A1

公开(公告)日：2014-04-17

申请号：US13947411

申请日：2013-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Jong-Mil Youn ,  Jong-Joon Park ,  Kwang-Yong Jang ,  Jun-Sun Hwang

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/518 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate, the insulating layer including a trench. A gate insulating layer is formed on a bottom surface of the trench and a reaction prevention layer is formed on the gate insulating layer on the bottom surface of the trench. A replacement metal gate structure is formed on the reaction prevention layer of the trench to fill the trench.

Abstract translation: 半导体器件包括形成在衬底上的层间绝缘膜，所述绝缘层包括沟槽。 在沟槽的底面上形成栅极绝缘层，在沟槽的底面上的栅极绝缘层上形成反应防止层。 在沟槽的反应防止层上形成替代金属栅极结构以填充沟槽。

公开(公告)号：US11581435B2

公开(公告)日：2023-02-14

申请号：US16895059

申请日：2020-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/165 ,  H01L27/02

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

公开(公告)号：US10714614B2

公开(公告)日：2020-07-14

申请号：US16109350

申请日：2018-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/165 ,  H01L27/02

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

公开(公告)号：US10084088B2

公开(公告)日：2018-09-25

申请号：US15618623

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/165 ,  H01L27/02

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.