公开(公告)号：US11271110B2

公开(公告)日：2022-03-08

申请号：US16693439

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jong Lee ,  Sanghyuk Hong ,  TaeYong Kwon ,  Sunjung Kim ,  Cheol Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L21/8238

Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods of fabricating the semiconductor devices may include providing a substrate including an active pattern protruding from the substrate, forming a first liner layer and a field isolating pattern on the substrate to cover a lower portion of the active pattern, forming a second liner layer on an upper portion of the active pattern and the field isolation pattern, and forming a dummy gate on the second liner layer.

公开(公告)号：US10128154B2

公开(公告)日：2018-11-13

申请号：US15674185

申请日：2017-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L27/088

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US09735059B2

公开(公告)日：2017-08-15

申请号：US14830199

申请日：2015-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

公开(公告)号：US09117910B2

公开(公告)日：2015-08-25

申请号：US14313435

申请日：2014-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heedon Jeong ,  Jae Yup Chung ,  Heesoo Kang ,  Donghyun Kim ,  Sanghyuk Hong ,  Soohun Hong

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7855

Abstract: A semiconductor device includes a fin region with long and short sides, a first field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the short side of the fin region, a second field insulating layer including a top surface lower than that of the fin region and adjacent to a side surface of the long side of the fin region, an etch barrier pattern on the first field insulating layer, a first gate on the fin region and the second field insulating layer to face a top surface of the fin region and side surfaces of the long sides of the fin region. A second gate is on the etch barrier pattern overlapping the first field insulating layer. A source/drain region is between the first gate and the second gate, in contact with the etch barrier pattern.

Abstract translation: 半导体器件包括具有短边和短边的鳍片区域，第一场绝缘层，其包括比翅片区域低的顶表面，并且与鳍片区域的短边的侧表面相邻;第二场绝缘层，包括 与翅片区域相比较靠近散热片区域的长边侧表面的顶表面，第一场绝缘层上的蚀刻阻挡图案，鳍状区域上的第一栅极和第二场绝缘层， 面对翅片区域的顶表面和翅片区域的长边的侧表面。 第二栅极位于与第一场绝缘层重叠的蚀刻阻挡图案上。 源极/漏极区在第一栅极和第二栅极之间，与蚀刻阻挡图案接触。