公开(公告)号：US20240311082A1

公开(公告)日：2024-09-19

申请号：US18194894

申请日：2023-04-03

申请人： Samsung Electronics Co., Ltd.

发明人： Saurabh Shankar ZOND ,  Debojyoti Banerjee ,  Abhishek Ghosh ,  Raghavendra Shirodkar ,  Rakesh Dimri ,  Yashaswini H G

IPC分类号： G06F7/501 ,  H03K19/20 ,  H03K19/21

CPC分类号： G06F7/501 ,  H03K19/20 ,  H03K19/215

摘要： Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.