公开(公告)号：US20240324185A1

公开(公告)日：2024-09-26

申请号：US18611395

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjae WON ,  Yoongoo KANG ,  Jaehong PARK

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485

Abstract: The present disclosure provides semiconductor devices including a bit line. In some embodiments, a semiconductor device includes a substrate including a plurality of active regions defined by device isolation layers, a plurality of bit lines extending in a first horizontal direction on the substrate, a bit line contact between a first active region of the plurality of active regions and a first bit line of the plurality of bit lines on the first active region, and an active pad on a second active region of the plurality of active regions adjacent to the first active region. The bit line contact includes a first contact layer and a second contact layer on the first contact layer. The active pad is disposed to face the bit line contact.

公开(公告)号：US20250048619A1

公开(公告)日：2025-02-06

申请号：US18421113

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Dongyoung KIM ,  Jaehong PARK ,  Seokjae WON

IPC: H10B12/00 ,  H01L23/528

Abstract: The present inventive concepts relate to semiconductor devices and methods for fabricating the same, and a semiconductor device according to some example embodiments includes: a substrate including an active region defined by a device isolation layer; a word line that crosses and overlaps the active region; a bit line crossing the active region in a direction different from the word line; a direct contact that connects the active region and the bit line and includes a metallic material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, wherein a width of the direct contact is different from that of the bit line, and the bit line spacer is on an upper surface of the direct contact.