公开(公告)号：US20190303148A1

公开(公告)日：2019-10-03

申请号：US16447035

申请日：2019-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F9/38

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

公开(公告)号：US10142139B2

公开(公告)日：2018-11-27

申请号：US15272994

申请日：2016-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Woo Ahn ,  Hyung Jong Kim ,  Hyun Woo Sim ,  Hun Kee Kim

IPC: G06F17/14 ,  H04L27/00 ,  G06F7/00 ,  G06F7/499

Abstract: A digital signal processor is provided. The digital signal processor includes an execution circuit configured to receive a first data including first bits expressed in a signed magnitude method and a second data including second bits expressed in the signed magnitude method, and a control logic circuit configured to output a control signal that determines a type of operation on the first data and the second data based on a command signal, wherein the execution circuit is further configured to perform an operation on the first data and the second data according to a determined type of operation and generate a result of the operation.

公开(公告)号：US11645072B2

公开(公告)日：2023-05-09

申请号：US17216323

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287 ,  G06T1/20

CPC classification number: G06F9/3001 ,  G06F1/3287 ,  G06F9/30101 ,  G06T1/20

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US10649771B2

公开(公告)日：2020-05-12

申请号：US15717989

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287 ,  G06T1/20

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US12106098B2

公开(公告)日：2024-10-01

申请号：US18129119

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287 ,  G06T1/20

CPC classification number: G06F9/3001 ,  G06F1/3287 ,  G06F9/30101 ,  G06T1/20 ,  G06T2207/20024 ,  G06T2207/20164

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US11442728B2

公开(公告)日：2022-09-13

申请号：US16447035

申请日：2019-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F9/38

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

公开(公告)号：US11068265B2

公开(公告)日：2021-07-20

申请号：US16447041

申请日：2019-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F9/38

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.

公开(公告)号：US10990388B2

公开(公告)日：2021-04-27

申请号：US16520761

申请日：2019-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287 ,  G06T1/20

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US10409593B2

公开(公告)日：2019-09-10

申请号：US15905979

申请日：2018-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F1/3287

Abstract: A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.

公开(公告)号：US10372451B2

公开(公告)日：2019-08-06

申请号：US15802844

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Pil Kim ,  Hyun Woo Sim ,  Seong Woo Ahn

IPC: G06F9/30 ,  G06F9/38

Abstract: A sequence alignment method that may be performed by a vector processor is may include loading a sequence that is an instance of vector data including a plurality of elements, dividing the sequence into two groups, aligning respective elements of the groups to generate a sequence of sorted elements according to a single instruction multiple data mode, and iteratively performing an alignment operation based on a determination that each group in the sequence of sorted elements includes more than one element of the plurality of elements. Each iteration may include dividing each group to form new groups and aligning respective elements of each pair of adjacent new groups to generate a new sequence of sorted elements. The new sequence of a current iteration of the alignment operation may be transmitted as a data output, based on a determination that each new group does not include more than one element.