公开(公告)号：US20240321876A1

公开(公告)日：2024-09-26

申请号：US18736793

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Ho SONG ,  Jong Han LEE ,  Jong Ha PARK ,  Jae Hyun LEE ,  Jong Hoon BAEK ,  Da Bok JEONG

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886

Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.

公开(公告)号：US20220059530A1

公开(公告)日：2022-02-24

申请号：US17405606

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Ho SONG ,  Jong Han LEE ,  Jong Ha PARK ,  Jae Hyun LEE ,  Jong Hoon BAEK ,  Da Bok JEONG

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device including a substrate including first and second regions along a first direction, and a third region between the first region and the second region, an active pattern extending in the first direction, on the substrate, and first to third gate electrodes spaced apart from each other and extending in a second direction, on the active pattern, the active pattern of the first region including first semiconductor patterns spaced apart from each other and penetrating the first gate electrode, the active pattern of the second region including second semiconductor patterns spaced apart from each other and penetrating the second gate electrode, the active pattern of the third region including a transition pattern protruding from the substrate and intersecting the third gate electrode and including a sacrificial pattern and a third semiconductor pattern alternately stacked on the third region and including different materials from each other.