公开(公告)号：US20230146377A1

公开(公告)日：2023-05-11

申请号：US17885822

申请日：2022-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Min YOU ,  Seong-Jin CHO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673 ,  G06F12/0238 ,  G06F2212/70

Abstract: According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.

公开(公告)号：US20230223073A1

公开(公告)日：2023-07-13

申请号：US17953524

申请日：2022-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung KIM ,  Jung Min YOU ,  Seong-Jin CHO

IPC: G11C11/4096 ,  G11C11/408 ,  G11C17/16

CPC classification number: G11C11/4096 ,  G11C11/408 ,  G11C17/165

Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

公开(公告)号：US20240185904A1

公开(公告)日：2024-06-06

申请号：US18232940

申请日：2023-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung KIM ,  Seong-Jin CHO

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C2211/4062

Abstract: A memory device includes a memory cell array including a plurality of rows, an ECC engine configured to determine a health level for each of the plurality of rows based on the number of corrections of errors of data read from each of the plurality of rows, a control logic configured to determine a victim row address based on the health level and the number of accesses for each of the plurality of rows, and a refresh control circuit configured to perform a refresh on a row corresponding to the determined victim row address.

公开(公告)号：US20220406368A1

公开(公告)日：2022-12-22

申请号：US17682257

申请日：2022-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hoon JUNG ,  Seong-Jin CHO

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/408

Abstract: A memory device is provided. The memory device includes a plurality of memory chips that are stacked, wherein each of the memory chips includes a memory cell array, which includes a plurality of memory cell rows, a chip identifier generator configured to generate a chip identifier signal indicating a chip identifier of each of the memory chips, a refresh counter configured to generate a target row address for refreshing the memory cell rows in response to a refresh command, and a target row address generator, which receives the chip identifier signal and the target row address and outputs one of the target row address and an inverted target row address, obtained by inverting the target row address, as a refresh row address based on the chip identifier signal, and performs a refresh operation on a memory cell row corresponding to the refresh row address.