公开(公告)号：US20250006137A1

公开(公告)日：2025-01-02

申请号：US18741906

申请日：2024-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heejin Lee ,  Minsung Kim ,  Sunkwon Kim ,  Seongyoung Ryu ,  Uijong Song ,  Yilho Lee ,  Yunrae Jo

IPC: G09G3/3275 ,  G09G3/00

Abstract: A display driving circuit includes a control logic, a source amplifier, and first and second switching elements. The source amplifier includes a first input terminal, a second input terminal, and an output terminal, and amplifies a pixel voltage for displaying an image on a display panel and provides the amplified pixel voltage to a pixel through a data line. The first switching element is connected between the first input terminal and the output terminal, and the second switching element is connected between the first input terminal and the sensing line. The control logic controls the first switching element and the second switching element such that the source amplifier compares a sample voltage that is input to the first input terminal through a sensing line with a comparison voltage input to the second input terminal and outputs comparison data based on the comparison.

公开(公告)号：US20230179394A1

公开(公告)日：2023-06-08

申请号：US18059522

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin KIM ,  Seongyoung Ryu ,  Soojoo Lee ,  Sengsub Chun ,  Hyunwoo Cho ,  Jongil Hwang

IPC: H04L7/00 ,  G06F1/08

CPC classification number: H04L7/0079 ,  H04L7/0008 ,  G06F1/08 ,  H03K19/20

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

公开(公告)号：US20250014515A1

公开(公告)日：2025-01-09

申请号：US18758335

申请日：2024-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkwon KIM ,  Uijong Song ,  Yongil Kwon ,  Seongyoung Ryu ,  Yilho Lee ,  Heejin Lee

IPC: G09G3/3233

Abstract: A display device includes pixels arranged in rows and columns, a scan driver, and a read-out circuit, wherein the read-out circuit is configured to read-out electrical properties of a pixel through the read-out line. The first pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first organic light-emitting diode connected between a second electrode of the seventh transistor and a ground node to which a ground voltage is applied, a second organic light-emitting diode between the second electrode of the eighth transistor and the ground node, and a third organic light-emitting diode connected between the second electrode of the ninth transistor and the ground node.

公开(公告)号：US12238195B2

公开(公告)日：2025-02-25

申请号：US18059522

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Seongyoung Ryu ,  Soojoo Lee ,  Sengsub Chun ,  Hyunwoo Cho ,  Jongil Hwang

IPC: H04L7/00 ,  G06F1/08 ,  G09G5/00 ,  H03K19/20

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

公开(公告)号：US12223905B2

公开(公告)日：2025-02-11

申请号：US18590365

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Uijong Song ,  Sunkwon Kim ,  Hyungjoong Kim ,  Seongyoung Ryu ,  Yilho Lee ,  Heejin Lee

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275 ,  H10K59/131

Abstract: A display apparatus includes plural pixels, a scan driver, a data driver, and a read-out circuit that reads out an electrical characteristic of each of the pixels. Each of the pixels includes a first transistor, a second transistor, a third transistor, a fourth transistor including a first electrode connected with a power node, a second electrode connected with a first node, and a gate connected with a first emission control line, a fifth transistor including a first electrode connected with a third node, a second electrode, and a gate connected with a second emission control line, a sixth transistor including a first electrode connected with a read-out line, a second electrode connected with the third node, and a gate connected a the read-out/initialization control line, a capacitor connected between the first node and the second node, and an organic light-emitting diode.