公开(公告)号：US20240397701A1

公开(公告)日：2024-11-28

申请号：US18637580

申请日：2024-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taejin Kim ,  Sungsoo Yim

IPC: H10B12/00

Abstract: A semiconductor device may include a bit line on a substrate, a bonding layer stacked on the bit line, a first conductive connection pattern stacked on the bonding structure layer, so that the bonding layer is vertically between the bit line and the first conductive layer, a channel stacked on the first conductive connection pattern and including a single crystalline semiconductor material, a second conductive connection pattern contacting the bit line and the first conductive connection pattern, a gate electrode on the bit line and being spaced apart from the channel and the first conductive connection pattern, and a capacitor stacked on the channel.

公开(公告)号：US12238195B2

公开(公告)日：2025-02-25

申请号：US18059522

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Seongyoung Ryu ,  Soojoo Lee ,  Sengsub Chun ,  Hyunwoo Cho ,  Jongil Hwang

IPC: H04L7/00 ,  G06F1/08 ,  G09G5/00 ,  H03K19/20

Abstract: A receiver circuit includes data lane modules, a clock lane module, a bias current controller and a link layer. Each of the data lane modules receive respective data signals. The clock lane module receives clock signals and provides each of the data lane modules with a respective divided clock signal among divided clock signals. The bias current controller controls a clock bias current. The link layer provides a bias control signal to the bias current controller and provides clock gating signals to the clock lane module, based on low power data signals and low power clock signals. The bias current controller, based on the bias control signal, provides the clock bias current having a first magnitude to the clock lane module in a second power mode and provides the clock bias current having a second magnitude to the clock lane module in a third power mode.

公开(公告)号：US20250040126A1

公开(公告)日：2025-01-30

申请号：US18670805

申请日：2024-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Kim ,  Taejin Park ,  Kyuchang Kang ,  Hyeonkyu Lee ,  Sungsoo Yim

IPC: H10B12/00

Abstract: A semiconductor device includes a lower circuit pattern, a bit line shield structure, a first insulating interlayer, a bit line structure, a first contact plug, a channel and a capacitor. The lower circuit pattern is on a substrate. The bit line shield structure is on the lower circuit pattern. The first insulating interlayer is in an opening extending through the bit line shield structure. The bit line structure is on the bit line shield structure, and at least partially overlaps the bit line shield structure in a vertical direction substantially perpendicular to an upper surface of the substrate. The first contact plug extends through the first insulating interlayer to contact the bit line structure, and is electrically connected to the lower circuit pattern. The channel is on the bit line structure. The capacitor is on the channel and is electrically connected to the channel.

公开(公告)号：US11271897B2

公开(公告)日：2022-03-08

申请号：US16504757

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soungkwan Kimn ,  Taejin Kim ,  Seung-Chull Suh

IPC: H04L29/12 ,  H04L61/2503

Abstract: An electronic apparatus includes a first translation table that stores information of a first address and a second address; a second translation table that, in response to a condition being satisfied, stores the information of the first address and the second address based on the first translation table; at least one processor configured to translate the first address of a first packet to the second address based on the first translation table; and a forwarding manager that, in response to a second packet including the first address being received and the information of the first address and the second address being stored in the second translation table, translates the first address of the second packet to the second address based on the second translation table, prior to allocating the second packet to the at least one processor.