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公开(公告)号：US20210375920A1
公开(公告)日：2021-12-02
申请号：US17176398
申请日：2021-02-16
发明人： Yujin Seo , Euntaek Jung , Byoungil Lee , Seul Lee , Joonhee Lee , Changdae Jung , Bonghyun Choi , Sejie Takaki
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11565 , H01L27/11526 , H01L27/11519
摘要： A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.
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公开(公告)号：US11856773B2
公开(公告)日：2023-12-26
申请号：US17176398
申请日：2021-02-16
发明人： Yujin Seo , Euntaek Jung , Byoungil Lee , Seul Lee , Joonhee Lee , Changdae Jung , Bonghyun Choi , Sejie Takaki
摘要： A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.
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公开(公告)号：US11967313B2
公开(公告)日：2024-04-23
申请号：US17385774
申请日：2021-07-26
CPC分类号： G10L15/183 , G06F40/58 , G10L15/063 , G10L15/16 , G10L15/22 , G10L15/30
摘要： Disclosed is a system comprising a memory storing a first natural language understanding model. The memory stores instructions that, when executed, cause a processor to: receive a request for generating a second natural language understanding model in a second language different from the first language; translate the first set of utterances into a second set of utterances in the second language; provide a second set of tags or intents to the second set of utterances; provide a user interface for receiving at least one input for modifying from among the second set of utterances or the second set of tags or intents; generate a third set of utterances and a third set of tags or intents on the basis of the input received through the user interface; and establish the second natural language understanding model including the third set of utterances and the third set of tags or intents.
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