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公开(公告)号：US20240081064A1
公开(公告)日：2024-03-07
申请号：US18452919
申请日：2023-08-21
发明人： Euntaek Jung , Sukkang Sung
摘要： According to some embodiments of the present disclosure, a semiconductor device is provided. A gate electrode structure includes a plurality of first gate electrode layers separated by interlayer insulating layers on a substrate. A plurality of first channel structures extend through the gate electrode structure. An insulating layer is on the first channel structures and the gate electrode structure. A second gate electrode layer is on the insulating layer. A plurality of second channel structures extends through the second gate electrode layer. Each of the second channel structures is electrically coupled with one of the first channel structures, and each of the second channel structures includes a first portion extending through the second gate electrode layer and a second portion on the first portion. The first portion has a first width, and the second portion has a second width that is greater than the first width.
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公开(公告)号：US10373673B2
公开(公告)日：2019-08-06
申请号：US15614714
申请日：2017-06-06
发明人： JoongShik Shin , Byoungil Lee , Hyunmog Park , Euntaek Jung
IPC分类号： H01L29/76 , G11C11/408 , G11C8/08 , G11C8/12 , G11C11/06 , H01L21/8239 , H01L23/528 , G11C8/14 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first peripheral circuit gate pattern. The substrate includes a cell array region and a peripheral circuit region. The ground selection line is on the cell array region. The word line is on the ground selection line. The insulating layer is between the ground selection line and the word line. The vertical channel portion penetrates the ground selection line, word line, and insulating layer in a direction vertical to a top surface of the substrate. The first peripheral circuit gate pattern is on the peripheral circuit region of the substrate. The insulating layer extends from the cell array region onto the peripheral circuit region to cover a top surface of the first peripheral circuit gate pattern.
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公开(公告)号：US11792982B2
公开(公告)日：2023-10-17
申请号：US17026377
申请日：2020-09-21
发明人： Woosung Yang , Hojun Seong , Joonhee Lee , Joon-Sung Lim , Euntaek Jung
IPC分类号： H01L27/11582 , H10B43/27 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/46 , H10B43/10 , H10B43/40
摘要： Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.
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公开(公告)号：US20220384480A1
公开(公告)日：2022-12-01
申请号：US17819355
申请日：2022-08-12
发明人： Euntaek Jung , JoongShik Shin , SangJun Hong
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11565 , H01L27/11575
摘要： A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
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公开(公告)号：US11063057B2
公开(公告)日：2021-07-13
申请号：US16152605
申请日：2018-10-05
发明人： Euntaek Jung , JoongShik Shin , Dongyoun Shin
IPC分类号： H01L27/115 , H01L27/11556 , H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L27/11524 , H01L27/11519
摘要： A three-dimensional semiconductor memory device includes a substrate, an electrode structure including a plurality of gate electrodes sequentially stacked on the substrate in a first direction that extends perpendicular to an upper surface of the substrate, a source conductive pattern between the substrate and the electrode structure, a vertical semiconductor pattern penetrating the electrode structure and the source conductive pattern, and a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure. A lower surface of the data storage pattern contacts the source conductive pattern. A portion of the lower surface of the data storage pattern is at a different height from the upper surface of the substrate, in relation to a height of another portion of the lower surface of the data storage pattern from the upper surface of the substrate.
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公开(公告)号：US10777572B2
公开(公告)日：2020-09-15
申请号：US16192859
申请日：2018-11-16
发明人： Euntaek Jung , JoongShik Shin , JiHye Yun
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L21/768 , H01L27/11573 , H01L23/528 , H01L23/532 , H01L21/285 , H01L27/1157 , H01L21/28 , H01L27/11548
摘要： A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.
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公开(公告)号：US12004350B2
公开(公告)日：2024-06-04
申请号：US17819355
申请日：2022-08-12
发明人： Euntaek Jung , Joongshik Shin , Sangjun Hong
摘要： A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
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公开(公告)号：US11437397B2
公开(公告)日：2022-09-06
申请号：US16139775
申请日：2018-09-24
发明人： Euntaek Jung , JoongShik Shin , SangJun Hong
IPC分类号： H01L29/792 , H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11565 , H01L27/11575 , H01L29/423
摘要： A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
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公开(公告)号：US20210375920A1
公开(公告)日：2021-12-02
申请号：US17176398
申请日：2021-02-16
发明人： Yujin Seo , Euntaek Jung , Byoungil Lee , Seul Lee , Joonhee Lee , Changdae Jung , Bonghyun Choi , Sejie Takaki
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11565 , H01L27/11526 , H01L27/11519
摘要： A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.
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公开(公告)号：US20190244970A1
公开(公告)日：2019-08-08
申请号：US16139775
申请日：2018-09-24
发明人： Euntaek Jung , JoongShik SHIN , SangJun HONG
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/1157
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573
摘要： A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.
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