公开(公告)号：US20230187439A1

公开(公告)日：2023-06-15

申请号：US17957654

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gun YOU ,  Sug Hyun SUNG ,  Chan Kyo PARK ,  Seung Chul OH

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/0673

Abstract: There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device comprising, a first active pattern on a substrate, the first active pattern including a first lower pattern, which extends in a first direction, and first sheet patterns, which are on the first lower pattern, a second active pattern on the substrate, the second active pattern including a second lower pattern, which is spaced apart from the first lower pattern in a second direction and a second sheet patterns, which are on the second lower pattern, wherein the first lower pattern and the second lower pattern is separated by a fin trench.

公开(公告)号：US20200075487A1

公开(公告)日：2020-03-05

申请号：US16285596

申请日：2019-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Wan SHIN ,  Ho Jun JUNG ,  Seung Chul OH

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56

Abstract: A fan-out semiconductor package includes a frame comprising wiring layers, and a dummy layer, and having a recessed portion on a bottom surface on which a stopper layer is disposed; a semiconductor chip disposed in the recessed portion such that an inactive surface opposes the stopper layer; a first interconnect structure disposed on the connection pad; a second interconnect structure disposed on the outermost wiring layer; a dummy structure disposed on the dummy layer; an encapsulant encapsulating at least portions of the frame, the semiconductor chip, the first interconnect structure, the second interconnect structure, and the dummy structure, and filling at least a portion of the recessed portion; and a connection member disposed on the frame and an active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to first and second metal bumps. The dummy structure has sloped side surfaces.