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公开(公告)号:US20220344272A1
公开(公告)日:2022-10-27
申请号:US17644716
申请日:2021-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chanmin Jo , Taeyoon Kim , Seungki Nam , Sungwook Moon
IPC: H01L23/538 , H01L25/18 , H01L25/065 , H01L21/48
Abstract: A semiconductor device includes pads of a first group and a plurality of first peripheral pads, which are adjacent to each other and spaced apart by a first horizontal gap in a first direction, and pads of a first group and a plurality of first peripheral pads, which are connected to each other and spaced apart by a first vertical gap, greater than the first horizontal gap, in a second direction. A plurality of first wiring patterns include first horizontal extension portions extending at an angle exceeding about 45 degrees with respect to the first direction within the first horizontal gap.
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公开(公告)号:US12057404B2
公开(公告)日:2024-08-06
申请号:US17644716
申请日:2021-12-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chanmin Jo , Taeyoon Kim , Seungki Nam , Sungwook Moon
IPC: H01L23/48 , H01L21/48 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/00 , H01L23/367 , H01L23/498
CPC classification number: H01L23/5386 , H01L21/486 , H01L25/0652 , H01L25/18 , H01L23/3675 , H01L23/49811 , H01L23/5384 , H01L24/16 , H01L2224/16227
Abstract: A semiconductor device includes pads of a first group and a plurality of first peripheral pads, which are adjacent to each other and spaced apart by a first horizontal gap in a first direction, and pads of a first group and a plurality of first peripheral pads, which are connected to each other and spaced apart by a first vertical gap, greater than the first horizontal gap, in a second direction. A plurality of first wiring patterns include first horizontal extension portions extending at an angle exceeding about 45 degrees with respect to the first direction within the first horizontal gap.
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公开(公告)号:US11205614B2
公开(公告)日:2021-12-21
申请号:US16863257
申请日:2020-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jun So Pak , Seungki Nam , Jiyoung Park , Bo Pu
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
Abstract: A stack package may include a first substrate package, a second substrate package, an interposer and at least one semiconductor chip. The first substrate package may include a plurality of first pads isolated from direct contact with each other by a first pitch. The second substrate package may be under the first substrate package. The second substrate package may include a plurality of second pads isolated from direct contact with each other by a second pitch. The second pitch may be different from the first pitch. The interposer may be above the first substrate package. The interposer may include a plurality of third pads isolated from direct contact with each other by a third pitch. The semiconductor chip may be arranged above the interposer.
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公开(公告)号:US11144699B2
公开(公告)日:2021-10-12
申请号:US17018262
申请日:2020-09-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungki Nam , Jungil Son , Sungwook Moon
IPC: G06F30/00 , G06F30/392 , G06F30/39
Abstract: Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.
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