公开(公告)号：US09922696B1

公开(公告)日：2018-03-20

申请号：US15425996

申请日：2017-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaungchen Li ,  Dimin Niu ,  Krishna Malladi ,  Hongzhong Zheng

IPC: G11C7/10 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4096

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

公开(公告)号：US10242728B2

公开(公告)日：2019-03-26

申请号：US15426033

申请日：2017-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaungchen Li ,  Dimin Niu ,  Krishna Malladi ,  Hongzhong Zheng

IPC: G06F12/00 ,  G11C11/406 ,  G06F15/80 ,  G06F9/38 ,  G11C7/10 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G06F15/78

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.

公开(公告)号：US10180808B2

公开(公告)日：2019-01-15

申请号：US15426015

申请日：2017-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shaungchen Li ,  Dimin Niu ,  Krishna Malladi ,  Hongzhong Zheng

IPC: G06F3/06 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4097

Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.