公开(公告)号：US20250107102A1

公开(公告)日：2025-03-27

申请号：US18620469

申请日：2024-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhoe KIM ,  Kilho LEE ,  Shin KWON ,  Hyeonah JO

IPC: H10B61/00 ,  G01R33/09 ,  H10N50/10

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a first lower insulating layer disposed on the cell region and extending onto the peripheral region, a second lower insulating layer disposed on the first lower insulating layer on the cell region and extending onto the first lower insulating layer on the peripheral region, data storage patterns disposed on the second lower insulating layer on the cell region, a cell insulating layer disposed on the second lower insulating layer on the cell region and covering the data storage patterns, and a peripheral insulating layer disposed on the second lower insulating layer on the peripheral region and including a material different from the cell insulating layer. A thickness of the second lower insulating layer on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region.

公开(公告)号：US20230139618A1

公开(公告)日：2023-05-04

申请号：US17862831

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungjae BAE ,  Shin KWON ,  Jeongmin PARK ,  Manjin EOM ,  Hyungjong JEONG

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.