公开(公告)号：US20190310587A1

公开(公告)日：2019-10-10

申请号：US16374236

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shin-woong KIM ,  Jae-young KIM ,  Chul-ho KIM ,  Jae-hyuk JANG ,  Sang-wook HAN

IPC: G04F10/00 ,  H04L7/00 ,  H04B17/14 ,  H03L7/08 ,  H03L7/089

Abstract: Provided is clock signal generator configured to generate a target output clock signal based on a reference clock signal, the clock signal generator includes a digital-to-time converter (DTC) configured to delay a reference clock signal based on an input code to generate a delay clock signal, and output the delay clock signal, a DTC controller configured to determine an initial gain value of the DTC based on a result of comparing at least one delay amount of the DTC with a period of a previously generated output clock signal, and generate the input code based on the initial gain value, and a phase locked loop configured to generate the target output clock signal based on the delay clock signal and a division clock signal of the previously generated output clock signal, the target output clock signal being locked to the delay clock signal.