公开(公告)号：US20180004281A1

公开(公告)日：2018-01-04

申请号：US15426526

申请日：2017-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Woon KANG ,  Siddharth KATARE ,  Jeong-Don IHM

IPC: G06F1/32 ,  G11C5/14 ,  G11C7/10

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/145 ,  G11C5/147 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  Y02D10/14

Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.