ELECTRONIC APPARATUS AND CONTROLLING METHOD THEREOF

    公开(公告)号:US20250142598A1

    公开(公告)日:2025-05-01

    申请号:US18893226

    申请日:2024-09-23

    Abstract: An electronic apparatus included in an Internet of Things (IoT) network includes a communication interface, and at least one processor. The at least one processor is configured to, based on occurrence of an event in which control information allowing control over a target apparatus be provided, identify a target apparatus among at least one external apparatus connected with the electronic apparatus, broadcast a packet in association with providing the control information through the communication interface, receive identification information from an apparatus that responds to the packet through the communication interface, and based on the received identification information from the apparatus being included in a pre-stored contact list, provide the control information allowing control over the target apparatus to the apparatus.

    METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    3.
    发明公开

    公开(公告)号:US20240196587A1

    公开(公告)日:2024-06-13

    申请号:US18229762

    申请日:2023-08-03

    CPC classification number: H10B12/02 H10B12/315 H10B12/482

    Abstract: A method of fabricating a semiconductor device include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit-line structure on the cell region, forming a preliminary pad layer covering the bit-line structure and the peripheral gate structure, and etching the preliminary pad layer to form a landing pad and a peripheral conductive pad. The etching the preliminary pad layer includes forming a first mask structure on the preliminary pad layer, forming a second mask structure on the first mask structure, forming a first photoresist layer on the second mask structure, and using the first photoresist layer as an etching mask to etch the second mask structure. The first photoresist layer includes a first line opening overlapping the cell region, and peripheral resist patterns overlapping the peripheral region.

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