公开(公告)号：US11443810B2

公开(公告)日：2022-09-13

申请号：US17220368

申请日：2021-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sooyeol Yang ,  Hyunggon Kim ,  Youngsun Song

IPC: G11C16/12 ,  H01L27/11582 ,  H01L27/11573

Abstract: A negative level shifter includes a shifting circuit and a latch circuit. The shifting circuit shifts levels of a first input signal and a second input signal to provide a first output signal and a second output signal having complementary levels at a first output node and a second output node, respectively, using low voltage transistors and high voltage transistors having different characteristics. The latch circuit, connected to the shifting circuit at the first output node and the second output node, latches the first output signal and the second output signal, receives a negative voltage having a level smaller than a ground voltage, and drives the second output signal and the first output signal complementarily to either a level of a power supply voltage or a level of the negative voltage, based on voltage levels at the first output node and the second output node, respectively.

公开(公告)号：US20250069961A1

公开(公告)日：2025-02-27

申请号：US18800813

申请日：2024-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyong Choi ,  Sooyeol Yang ,  Jaeeun Lee ,  Hyuckjoon Kwon ,  Jinwon Choi ,  Takuya Futatsuyama

IPC: H01L21/66 ,  G01R31/28

Abstract: A semiconductor multi-layer structure includes a first semiconductor wafer including a plurality of first pads, a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads, and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.