公开(公告)号：US20230361018A1

公开(公告)日：2023-11-09

申请号：US18166181

申请日：2023-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin YIM ,  Sungbum KIM ,  Jiyong PARK ,  Jinwoo PARK ,  Jongbo SHIM

IPC: H01L23/498 ,  H10B80/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H10B80/00 ,  H01L24/16

Abstract: Provided is a semiconductor package including a support wiring structure, a semiconductor chip on the support wiring structure, a cover wiring structure on the semiconductor chip, and a filling member filling between the support wiring structure and the cover wiring structure, wherein the cover wiring structure includes a cavity which extends from a lower surface of the cover wiring structure into the cover wiring structure and in which an upper portion of the semiconductor chip is positioned, and a first slot and a second slot respectively having a first width and a second width in a first horizontal direction, the first slot and the second slot communicating with the cavity, and respectively extending to a first side surface and a second side surface of the cover wiring structure, which are opposite to each other in a second horizontal direction which is orthogonal to the first horizontal direction of the cover wiring structure.

公开(公告)号：US20230361051A1

公开(公告)日：2023-11-09

申请号：US18113910

申请日：2023-02-24

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Choongbin YIM ,  Hyonchol KIM ,  Sungbum KIM ,  Gitae PARK ,  Jiyong PARK ,  Jinwoo PARK ,  Jongbo SHIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/16 ,  H01L21/4853 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81815

Abstract: A semiconductor package includes: a package substrate including a redistribution layer, a lower protective layer, and a plurality of support protrusions, wherein the redistribution layer has first and second pads disposed on the package substrate, wherein the lower protective layer has first openings and a trench, wherein the trench exposes the second pads, and wherein the plurality of support protrusions are disposed in the trench; a semiconductor chip disposed on the package substrate and including connection pads electrically connected to the redistribution layer; an encapsulant disposed on at least a portion of the semiconductor chip; first connection bumps electrically connected to the first pads, respectively; a passive device disposed in the trench of the lower protective layer and electrically connected to the second pads; and a sealant covering at least a portion of the passive device and extending into the trench.

公开(公告)号：US20210183780A1

公开(公告)日：2021-06-17

申请号：US17096107

申请日：2020-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungbum KIM ,  Taewoo KANG ,  Jaewon CHOI

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.