公开(公告)号：US20230096746A1

公开(公告)日：2023-03-30

申请号：US17849945

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungil WOO ,  Sungcheol PARK ,  Jehyun PARK

IPC: G01R31/317 ,  G01R31/3185

Abstract: A semiconductor integrated circuit to receive a test scan input, a test clock, and a test mode signal and output a secure scan output signal, the integrated circuit including: a secure key circuit to generate delay input signals, which are differently delayed from the test scan input, and to generate an input key signal by capturing the delay input signals in response to the test clock; a key comparator to generate a verification result indicating whether an input key of the input key signal is identical with a preset reference key; a chip to generate a scan output signal based on the test scan input; a scan output remapper to obfuscate the scan output signal according to the verification result and to output the obfuscated scan output signal as the secure scan output signal; and a secure scan controller to control the secure key circuit, key comparator, chip, and remapper.

公开(公告)号：US20250103488A1

公开(公告)日：2025-03-27

申请号：US18898068

申请日：2024-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mingoo KANG ,  Joonyoung CHANG ,  Sungcheol PARK

IPC: G06F12/02

Abstract: A compute express link (CXL) memory device may include a high bandwidth memory (HBM) comprising a CXL base die and a plurality of core dies that are sequentially stacked on the CXL base die. The CXL base die may include an HMB interface intellectual property (IP) core configured to convert data transmission and reception between the plurality of core dies and dynamic random access memory (DRAM) in compliance with a CXL specification, and the HMB interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard.

公开(公告)号：US20250103787A1

公开(公告)日：2025-03-27

申请号：US18824006

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsu LEE ,  Wontae JEONG ,  Sungcheol PARK

IPC: G06F30/3953

Abstract: A routing method for an integrated circuit includes selecting design for testing (DFT) instances targeted by routing, routing positions respectively corresponding to the DFT instances, generating routing sequences for the DFT instances, deriving a start point and an end point based on indices included in each of the routing sequences, calculating a distance between the start point and the end point, and selecting a routing sequence as a result of the calculating of the distance.

公开(公告)号：US20240426909A1

公开(公告)日：2024-12-26

申请号：US18659942

申请日：2024-05-09

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Sangsoon IM ,  Sungcheol PARK

IPC: G01R31/3185

Abstract: Provided are a logic built-in self-test (BIST) circuit that performs a scan test improving test coverage for each clock domain and a semiconductor device including the logic BIST circuit. The logic BIST circuit includes an OR gate configured to receive a scan enable signal and a register setting signal, and generate a modified scan enable signal; a clock gating circuit configured to output an enable clock irrespective of a function enable signal when the register setting signal has a first logic value, and a scan chain configured to capture an output of a first logic circuit connected to flip-flops according to the enable clock.