公开(公告)号：US08563390B2

公开(公告)日：2013-10-22

申请号：US13868752

申请日：2013-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsoo Kim ,  Yoonkyung Choi ,  Eun Young Lee ,  Sungil Jo

IPC: H01L21/20 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/60 ,  H01L29/861 ,  H01L29/94

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract translation: 半导体器件包括并联连接的电容器。 电极活性部分和放电活性部分限定在半导体衬底上，并且封盖电极分别设置在电极活性部分上。 在每个封盖电极和彼此重叠的每个电极活性部分之间设置电容器 - 电介质层。 反向掺杂区域设置在放电有源部分中。 下部层间电介质覆盖半导体衬底的整个表面。 电极接触插头分别通过下层间电介质接触封盖电极，并且放电接触插塞通过下层间电介质接触反掺杂区域。 较低的互连布置在下层间电介质上并与电极接触插塞和放电接触插头接触。

公开(公告)号：US20130230963A1

公开(公告)日：2013-09-05

申请号：US13868752

申请日：2013-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myoungsoo Kim ,  Yoonkyung Choi ,  Eun Young Lee ,  Sungil Jo

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L29/861 ,  H01L29/94

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract translation: 半导体器件包括并联连接的电容器。 电极活性部分和放电活性部分限定在半导体衬底上，并且封盖电极分别设置在电极活性部分上。 在每个封盖电极和彼此重叠的每个电极活性部分之间设置电容器 - 电介质层。 反向掺杂区域设置在放电有源部分中。 下部层间电介质覆盖半导体衬底的整个表面。 电极接触插头分别通过下层间电介质接触封盖电极，并且放电接触插塞通过下层间电介质接触反掺杂区域。 较低的互连布置在下层间电介质上并与电极接触插塞和放电接触插头接触。