公开(公告)号：US20230378315A1

公开(公告)日：2023-11-23

申请号：US18060037

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsoo Kim ,  Seongheon Woo ,  Youngchan Lee ,  Jungmin Hyun

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/266

Abstract: A manufacturing method of a semiconductor device including forming a photoresist pattern on a semiconductor substrate on which a gate electrode has been formed, forming a well region using both the photoresist pattern and the gate electrode as a mask, forming a lightly doped drain (LDD) region in the well region, using both the photoresist pattern and the gate electrode as a mask, reducing a thickness of the photoresist pattern by removing a portion of the photoresist pattern, forming a halo region below the LDD region using both the photoresist pattern and the gate electrode as a mask, and removing the photoresist pattern.

公开(公告)号：US12016109B2

公开(公告)日：2024-06-18

申请号：US17748152

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyun Lee ,  Myoungsoo Kim ,  Sangchul Han ,  Daeman Seo

IPC: H05H1/46

CPC classification number: H05H1/466

Abstract: A plasma generator includes a coaxial tube assembly, a radio frequency (RF) electrode, and a feed including an inner circumferential surface that defines a first and second recesses at opposite, first and second ends of the feed. A first protrusion of the coaxial tube assembly is coupled to the first recess of the feed. A second protrusion of the coaxial tube assembly is coupled to the second recess of the feed. The feed includes first and second inner surfaces that define first and second insertion grooves in the inner circumferential surface at the first and second ends of the feed, respectively. First and second coil springs are at least partially within the first and second insertion grooves, respectively. The coaxial tube assembly, the RF electrode, and the feed provide an RF power transmission path based on the feed being coupled between the coaxial tube assembly and the RF electrode.

公开(公告)号：US08563390B2

公开(公告)日：2013-10-22

申请号：US13868752

申请日：2013-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsoo Kim ,  Yoonkyung Choi ,  Eun Young Lee ,  Sungil Jo

IPC: H01L21/20 ,  H01L27/108 ,  H01L29/94

CPC classification number: H01L28/60 ,  H01L29/861 ,  H01L29/94

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract translation: 半导体器件包括并联连接的电容器。 电极活性部分和放电活性部分限定在半导体衬底上，并且封盖电极分别设置在电极活性部分上。 在每个封盖电极和彼此重叠的每个电极活性部分之间设置电容器 - 电介质层。 反向掺杂区域设置在放电有源部分中。 下部层间电介质覆盖半导体衬底的整个表面。 电极接触插头分别通过下层间电介质接触封盖电极，并且放电接触插塞通过下层间电介质接触反掺杂区域。 较低的互连布置在下层间电介质上并与电极接触插塞和放电接触插头接触。

公开(公告)号：US11374202B2

公开(公告)日：2022-06-28

申请号：US16877303

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsoo Kim

IPC: H01L51/52 ,  H01L51/56 ,  H01L27/32

Abstract: A light emitting device includes a substrate; a circuit region including a circuit device on the substrate; an insulating layer on the circuit region; a first light emitting region connecting portion, a second light emitting region connecting portion, and a third light emitting region connecting portion, in the insulating layer; and a light emitting portion including a first light emitting region on the first light emitting region connecting portion, a second light emitting region on the second light emitting region connecting portion, and a third light emitting region on the third light emitting region connecting portion, the first light emitting region connecting portion includes first light reflective layers including a first lower light reflective layer, a first intermediate light reflective layer on the first lower light reflective layer, and a first upper light reflective layer on the first intermediate light reflective layer, and at least one first via plug connected to the first light emitting region, the second light emitting region connecting portion includes second light reflective layers including a second lower light reflective layer, and a second upper light reflective layer on the second lower light reflective layer, and at least one second via plug connected to the second light emitting region, and the third light emitting region connecting portion includes a third light reflective layer, and a third via plug connected to the third light emitting region.

公开(公告)号：US11362145B2

公开(公告)日：2022-06-14

申请号：US16782260

申请日：2020-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoungsoo Kim

IPC: H01L27/32 ,  H01L51/52

Abstract: An OLED including a substrate; a circuit region; reflective metal layers on the circuit region and including first to third reflective metal layers spaced apart from each other; an insulating layer including first to third insulating regions covering upper surfaces of the reflective metal layers and having a first to third thicknesses that are different from one another; first to third via plugs penetrating through the insulating layer to contact the reflective metal layers, first electrodes in contact with the via plugs, and covering a portion of an upper surface of the insulating layer; an organic light emitting layer on the first electrodes; and a second electrode on the organic light emitting layer, wherein the first to third via plugs include tungsten.

公开(公告)号：US20230299016A1

公开(公告)日：2023-09-21

申请号：US18110233

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoungsoo Kim ,  Jisung Kim

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/564 ,  H01L2224/0401 ,  H01L24/05 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13171 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L24/13

Abstract: A semiconductor device includes a substrate including a circuit region and a protection region surrounding the circuit region, a plurality of insulating layers sequentially provided on the substrate, a moisture blocking structure extending in the plurality of insulating layers in the protection region of the substrate and surrounding the circuit region, the moisture blocking structure including a first plurality of wiring layers vertically provided on a surface of the substrate, where an uppermost wiring layer of the first plurality of wiring layers comprises a first via, and a metal wiring provided on the first via, and a crack stopper extending in the plurality of insulating layers in the protection region of the substrate and surrounding the moisture blocking structure, the crack stopper including a second plurality of wiring layers vertically provided on the surface of the substrate.

公开(公告)号：US10026819B2

公开(公告)日：2018-07-17

申请号：US15626573

申请日：2017-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoungsoo Kim

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3213

Abstract: The semiconductor device including a device isolation layer disposed in a substrate and defining an active region, a first conductive pattern on the active region, an impurity region in the active region on a side of the first conductive pattern, a second conductive pattern on the active region between the impurity region and the first conductive pattern, a first spacer between the first conductive pattern and the second conductive pattern, and a contact plug disposed on and electrically connected to the first conductive pattern may be provided. The second conductive pattern may have a width less than a width of the contact plug.

公开(公告)号：US20130230963A1

公开(公告)日：2013-09-05

申请号：US13868752

申请日：2013-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myoungsoo Kim ,  Yoonkyung Choi ,  Eun Young Lee ,  Sungil Jo

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L29/861 ,  H01L29/94

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract translation: 半导体器件包括并联连接的电容器。 电极活性部分和放电活性部分限定在半导体衬底上，并且封盖电极分别设置在电极活性部分上。 在每个封盖电极和彼此重叠的每个电极活性部分之间设置电容器 - 电介质层。 反向掺杂区域设置在放电有源部分中。 下部层间电介质覆盖半导体衬底的整个表面。 电极接触插头分别通过下层间电介质接触封盖电极，并且放电接触插塞通过下层间电介质接触反掺杂区域。 较低的互连布置在下层间电介质上并与电极接触插塞和放电接触插头接触。