公开(公告)号：US10242984B2

公开(公告)日：2019-03-26

申请号：US15614911

申请日：2017-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Sutae Kim ,  Donghyun Kim ,  Ha-Young Kim ,  Jung-ho Do ,  Sunyoung Park ,  Sanghoon Baek ,  Jaewan Choi

IPC: H01L27/02 ,  H01L27/092 ,  H01L21/8238

Abstract: According to example embodiments, a semiconductor device and a method for manufacturing the same are provided, the semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.

公开(公告)号：US10943923B2

公开(公告)日：2021-03-09

申请号：US16574339

申请日：2019-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Jeong ,  Jiwook Kwon ,  Sutae Kim ,  Hyelim Kim

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

公开(公告)号：US20240421082A1

公开(公告)日：2024-12-19

申请号：US18662042

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeon Won Jeong ,  Yubo Qian ,  Sutae Kim ,  Jae Young Park ,  Jin Woo Lee

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a substrate including a standard cell area and an ending cell area that at least partially surrounds the standard cell area; a first active pattern in the standard cell area; a first wiring that extends in a first direction and is on the first active pattern; a first gate electrode that extends in a second direction and is on the first active pattern; a first gate contact; a second active pattern in the ending cell area; a second wiring that extends in the first direction and is on the second active pattern; a second gate electrode that extends in the second direction and is on the second active pattern; and a second gate contact.

公开(公告)号：US20150234974A1

公开(公告)日：2015-08-20

申请号：US14181990

申请日：2014-02-17

Applicant: Samsung Electronics Co., Ltd. ,  International Business Machines Corporation

Inventor： Daniel J. Dechene ,  Sutae Kim ,  Chieh-yu Lin

IPC: G06F17/50

Abstract: A three color map can be built based on an integrated circuit (IC) layout, each color representing an exposure in a multiple (here triple) patterning lithography process and can include any combination of additive and/or subtractive exposures. A series of design rules can start with color-specific rules before considering any combination of colors and/or exposures. If the map fails any rule, building the map can be repeated with adjustments and it can be assessed with the design rules.

Abstract translation: 可以基于集成电路（IC）布局构建三色图，每种颜色表示在多重（这里是三重）图案化光刻工艺中的曝光，并且可以包括添加和/或减影曝光的任何组合。 在考虑颜色和/或曝光的任何组合之前，一系列设计规则可以从颜色特定的规则开始。 如果地图没有任何规则，建造地图可以重复进行调整，并可以用设计规则进行评估。