公开(公告)号：US10128148B2

公开(公告)日：2018-11-13

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha Nguyen ,  Nae In Lee ,  Thomas Oszinda ,  Byung Hee Kim ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L21/768

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US10096549B2

公开(公告)日：2018-10-09

申请号：US15480055

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hee Kim ,  Thomas Oszinda ,  Deok Young Jung ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.

公开(公告)号：US20180076140A1

公开(公告)日：2018-03-15

申请号：US15480055

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hee KIM ,  Thomas Oszinda ,  Deok Young Jung ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.