公开(公告)号：US12080358B2

公开(公告)日：2024-09-03

申请号：US17866904

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Kil Jung ,  Sang-Wan Nam ,  Jong Min Baek ,  Min Ki Jeon ,  Woo Chul Jung ,  Yoon-Hee Choi

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device including a memory cell array, a first voltage generator configured to generate a word line operating voltage for each word line of the memory cell array, a second voltage generator configured to generate a bit line operating voltage of the memory cell array, and a temperature unit configured to determine, from a temperature range table, a temperature range for a temperature code according to a real-time temperature of the memory cell array, and to adjust a power supply voltage of the first or second voltage generator based on a selection signal mapped to the determined temperature range.

公开(公告)号：US20230307370A1

公开(公告)日：2023-09-28

申请号：US17968050

申请日：2022-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang Ho Lee ,  Woo Kyung You ,  Jong Min Baek

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895

Abstract: A semiconductor device is provided. The semiconductor device includes a first interlayer insulating layer, a lower wiring disposed inside the first interlayer insulating layer, an etching stop layer which includes first to third layers sequentially stacked on the first interlayer insulating layer, a second interlayer insulating layer disposed on the etching stop layer, and a via which penetrates the second interlayer insulating layer and the etching stop layer, the via is connected to the lower wiring, the via includes a first side wall that is in contact with the second layer, and a second side wall that is in contact with the second interlayer insulating layer, the via includes a first protrusion protruding in a horizontal direction from the first side wall inside the first layer, and a second protrusion protruding in the horizontal direction from the first side wall inside the third layer.

公开(公告)号：US11348827B2

公开(公告)日：2022-05-31

申请号：US16798789

申请日：2020-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US10804145B2

公开(公告)日：2020-10-13

申请号：US16545150

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong Gil Kim ,  Han Seong Kim ,  Jong Min Baek ,  Ji Young Kim ,  Sung Bin Park ,  Deok Young Jung ,  Kyu Hee Han

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

公开(公告)号：US10128148B2

公开(公告)日：2018-11-13

申请号：US15636889

申请日：2017-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Viet Ha Nguyen ,  Nae In Lee ,  Thomas Oszinda ,  Byung Hee Kim ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L21/768

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.

公开(公告)号：US10096549B2

公开(公告)日：2018-10-09

申请号：US15480055

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hee Kim ,  Thomas Oszinda ,  Deok Young Jung ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.

公开(公告)号：US20180076140A1

公开(公告)日：2018-03-15

申请号：US15480055

申请日：2017-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Hee KIM ,  Thomas Oszinda ,  Deok Young Jung ,  Jong Min Baek ,  Tae Jin Yim

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.

公开(公告)号：US20250063814A1

公开(公告)日：2025-02-20

申请号：US18661872

申请日：2024-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Rak Hwan Kim ,  Jong Min Baek

IPC: H01L27/118

Abstract: A semiconductor device includes a substrate; a first transistor on the substrate; a first contact on a source/drain pattern of the first transistor; a second transistor on the substrate; a second contact on a gate electrode of the second transistor; a first connecting structure that includes at least one first wiring and at least one first via that are alternately stacked on the first contact; a second connecting structure that includes at least one second wiring and at least one second via that are alternately stacked on the second contact; a first connecting via on the first connecting structure; a second connecting via on the second connecting structure; and a connecting wiring on the first connecting via and the second connecting via.

公开(公告)号：US12218002B2

公开(公告)日：2025-02-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin Kang ,  Jong Min Baek ,  Woo Kyung You ,  Kyu-Hee Han ,  Han Seong Kim ,  Jang Ho Lee ,  Sang Shin Jang

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20240355637A1

公开(公告)日：2024-10-24

申请号：US18476390

申请日：2023-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： John Soo Kim ,  Gwan Ho Kim ,  Ji Yoon Kim ,  Heung Sik Park ,  Keun Hee Bai ,  Jong Min Baek ,  Do Haing Lee ,  Jong Sun Lee

IPC: H01L21/32 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/32 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/76831

Abstract: A for fabricating a semiconductor device comprises forming a mask layer on a substrate, the mask layer defining a through hole that exposes an upper surface of the substrate, the mask layer comprising a first mask layer and a second mask layer, wherein the second mask layer is between the substrate and the first mask layer, and wherein the second mask layer comprises carbon. The method includes forming a liner layer on side walls of the through hole inside the second mask layer.