公开(公告)号：US10733349B2

公开(公告)日：2020-08-04

申请号：US16136497

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHee Lee

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/34 ,  G06F30/394

Abstract: A method for fabricating a semiconductor chip includes placing, at a processor, a target cell to be used for a design of the semiconductor chip depending on a first placement, changing, at the processor, the first placement to a second placement, based on a result of comparing a cost function value of the target cell in the first placement with a reference value, and fabricating the semiconductor chip based on one of the first placement and the second placement.

公开(公告)号：US20190251222A1

公开(公告)日：2019-08-15

申请号：US16136497

申请日：2018-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHee Lee

IPC: G06F17/50

Abstract: A method for fabricating a semiconductor chip includes placing, at a processor, a target cell to be used for a design of the semiconductor chip depending on a first placement, changing, at the processor, the first placement to a second placement, based on a result of comparing a cost function value of the target cell in the first placement with a reference value, and fabricating the semiconductor chip based on one of the first placement and the second placement.

公开(公告)号：US10720441B2

公开(公告)日：2020-07-21

申请号：US15988745

申请日：2018-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee-Sung Kam ,  TaeHee Lee ,  Kyoung-Hoon Kim

IPC: H01L21/82 ,  H01L27/11582 ,  G11C16/08 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/04

Abstract: Provided is a three-dimensional semiconductor memory device. The device may include a substrate that includes a cell array region and a connection region; an electrode structure provided on the substrate to extend in a first direction and include electrodes that are vertically stacked on the substrate and include pad portions which are stacked on the connection region to have a staircase structure; cell vertical structures provided on the cell array region to penetrate the electrode structure; dummy vertical structures provided on the connection region to penetrate the pad portion of each electrode; and cell contact plugs coupled to the pad portions of the electrodes. Each cell contact plug may have a non-circular top surface, and the dummy vertical structures may be arranged to surround each cell contact plug, in a plan view.

公开(公告)号：US10043822B2

公开(公告)日：2018-08-07

申请号：US15706861

申请日：2017-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHee Lee ,  Kyoung-Hoon Kim ,  Hongsoo Kim

IPC: H01L29/792 ,  H01L27/11582

Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

公开(公告)号：US10546869B2

公开(公告)日：2020-01-28

申请号：US15800545

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekeun Cho ,  Hongsoo Kim ,  Jong-Kook Park ,  TaeHee Lee

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.

公开(公告)号：US20180294225A1

公开(公告)日：2018-10-11

申请号：US15855416

申请日：2017-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： TaeHee Lee ,  Juyeon LEE ,  Jeehoon HWANG

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573

Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate a substrate including a peripheral circuit region and a cell array region, an electrode structure including a plurality of electrodes vertically stacked on the cell array region of the substrate, a peripheral logic circuit provided on the peripheral circuit region of the substrate, the peripheral logic circuit including a first impurity region doped with first impurities, a peripheral contact plug connected to the first impurity region, and a second impurity region between the first impurity region and the peripheral contact plug, the second impurity region being including second impurities different from the first impurities. The peripheral contact plug includes a lower portion contacting the second impurity region, and an upper portion continuously extending from the lower portion a lower width of each of the lower and upper portions is less than an upper width thereof, and the upper width of the lower portion is greater than the lower width of the upper portion.

公开(公告)号：US20180261616A1

公开(公告)日：2018-09-13

申请号：US15800545

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekeun Cho ,  Hongsoo Kim ,  Jong-Kook Park ,  TaeHee Lee

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L27/11578 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.