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公开(公告)号:US11430080B2
公开(公告)日:2022-08-30
申请号:US16931435
申请日:2020-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Veynu Narasiman , David Tannenbaum , Keshavan Varadarajan
Abstract: A method of executing an early-Z draw call in a graphics processing pipeline may include detecting a late-Z draw call in the pipeline, determining a compatibility of a depth comparison function of the early-Z draw call with a depth comparison function of the late-Z draw call, and speculatively executing a fragment of the early-Z draw call with a shader. The method may further include determining that the fragment of the early-Z draw call passes the depth comparison function of the early-Z draw call, and updating a depth buffer with a depth value for the fragment of the early-Z draw call. The method may further include determining that the fragment of the early-Z draw call provides a correct result, and forwarding the speculative shader result for the fragment to a next stage of the pipeline.
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公开(公告)号:US11798218B2
公开(公告)日:2023-10-24
申请号:US17503259
申请日:2021-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Keshavan Varadarajan , Veynu Narasiman , David C. Tannenbaum
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T2210/21
Abstract: A method of packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique. The indication may include one or more of: an importance, a quality, a level of interest, a level of detail, or a variable-rate shading (VRS) level. The indication may be received from an application. The packing technique may include array merging. The array merging may include quad merging. The packing technique may include pixel piling. The packing technique may be a first packing technique, and the method may further include determining, based on the indication, a second packing technique for the portion of the image, and packing coverage for the portion of the image based on the second packing technique.
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公开(公告)号:US11416960B2
公开(公告)日:2022-08-16
申请号:US17110284
申请日:2020-12-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: David C. Tannenbaum , Keshavan Varadarajan , Veynu Narasiman
Abstract: A binning subsystem of a GPU includes a storage subsystem, a shader core to output first data via a first path, a selector to receive the first data via the first path, and to receive second data from the storage subsystem via a second path. The storage subsystem includes a binner unit and a control logic unit. The control logic unit causes the selector to transfer the first data or the second data to the binner unit. The binner unit may transfer binner output data to the shader core via a third path. The binner unit may transfer the binner output data to one or more subsequent stages of a graphics pipeline via a fourth path. The binner unit may transfer the binner output data to the storage subsystem via a fifth path. The control logic unit may control the binner unit such that the binner unit can be used for general purpose computation.
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