公开(公告)号：US20170123700A1

公开(公告)日：2017-05-04

申请号：US15336772

申请日：2016-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vikas K. SINHA ,  Gunneswara Rao MARRIPUDI ,  Jianjian HUO ,  Ajit YAGATY

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0253 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/065 ,  G06F3/067 ,  G06F2212/702

Abstract: A distributed storage system node (125, 130, 135) is disclosed. The distributed storage system node (125, 130, 135) may include at least one storage device (140, 145, 150, 155, 160, 165, 225, 230), which may act as the primary replica (2315) for data subject to an Input/Output (I/O) request (905). A cost analyzer (2310) may calculate a local estimated time required (3305) to complete the I/O request (905) at the primary replica, and a remote estimated time required (3710) to complete the I/O request (905) at a secondary replica (2320, 2325) of the data. An I/O redirector (215) may direct the I/O request (905) to either the primary replica (2315) or the secondary replica (2320, 2325) based on the local estimated time required (3305) and the one remote estimated time required (3710).

公开(公告)号：US20150268961A1

公开(公告)日：2015-09-24

申请号：US14463638

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gerald D. ZURASKI ,  Vikas K. SINHA ,  David M. MIELKE ,  Paul E. KITCHIN

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3806 ,  G06F9/3804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/6022

Abstract: According to one general aspect, a method may include requesting, from a second tier of a cache memory system, a first instruction stored at a first memory address. The method may also include requesting, from a second tier of a branch target buffer system, a branch record associated with the first memory address. The method may also include receiving the branch record before receiving the first instruction. The method may also include pre-fetching, in response to receiving the branch record and before receiving the first instruction, a non-sequential instruction stored at a non-sequential memory address.

Abstract translation: 根据一个一般方面，一种方法可以包括从高速缓冲存储器系统的第二层请求存储在第一存储器地址处的第一指令。 该方法还可以包括从分支目标缓冲器系统的第二层请求与第一存储器地址相关联的分支记录。 该方法还可以包括在接收第一指令之前接收分支记录。 该方法还可以包括：响应于接收到分支记录并在接收到第一指令之前预取存储在非顺序存储器地址处的非顺序指令。