公开(公告)号：US20210279064A1

公开(公告)日：2021-09-09

申请号：US16882018

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Richard N. Deglin ,  Yash Jajoo ,  Vulligadla Amaresh ,  Jihyun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54 ,  G06F13/42 ,  G06F13/40

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.

公开(公告)号：US10108371B2

公开(公告)日：2018-10-23

申请号：US15489853

申请日：2017-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Venkataratnam Nimmagadda ,  Vulligadla Amaresh

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A solid state storage device including a non-volatile memory Express (NVMe) controller and configured to manage a Host Memory Buffer (HMB) in a host may be provided. The NVMe controller may be configured to fetch HMB descriptor entries as part of a feature command from the host, partition the HMB logically into a control buffer partition and a data buffer partition, store the HMB descriptor entries pointing to the control buffer partition within the solid state storage device as an HMB pointer list table, and write-back the HMB descriptor entries pointing to the data buffer partition into the control buffer partition of HMB.

公开(公告)号：US11960350B2

公开(公告)日：2024-04-16

申请号：US17817476

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiran Kumar Muralidharan ,  Srinivasa Raju Nadakuditi ,  Vulligadla Amaresh

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0706 ,  G06F11/0781 ,  G06F11/0793

Abstract: A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.

公开(公告)号：US20230053582A1

公开(公告)日：2023-02-23

申请号：US17817476

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiran Kumar MURALIDHARAN ,  Srinivasa Raju Nadakuditi ,  Vulligadla Amaresh

IPC: G06F11/07

Abstract: A system for error reporting and handling includes a memory storing an error handler, a processor configured to execute the error handler, and a buffer. The error handler is configured to receive an error message from a system on chip (SOC) platform. The error message indicates a plurality of errors have occurred in the SOC platform, and the buffer stores the error message. Further, the error handler is configured to report the error message using a single interrupt. Further, the error handler is configured to handle the errors in the error message using the single interrupt.

公开(公告)号：US11231934B2

公开(公告)日：2022-01-25

申请号：US16882018

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Richard N. Deglin ,  Yash Jajoo ,  Vulligadla Amaresh ,  Jihyun Kim

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/40 ,  G06F13/42 ,  G06F9/54

Abstract: A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.