公开(公告)号：US20240329986A1

公开(公告)日：2024-10-03

申请号：US18737945

申请日：2024-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Abhay Raj Kumar GUPTA ,  Wilson Wai Lun FUNG

IPC: G06F9/30 ,  G06F9/38 ,  G06F16/172 ,  G06T1/20

CPC classification number: G06F9/30036 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/3826 ,  G06F9/3858 ,  G06F16/172 ,  G06T1/20

Abstract: A method for performing opportunistic write-back discard of single-use vector register values. The method includes executing instructions of a GPU in a default mode, detecting a beginning of a single-use section that includes instructions that produce single-use vector register values, and executing instructions in a single-use mode. The method includes discarding the write-back of a single-use vector register value if the single-use value gets forwarded either via a bypass path or via register file cache. The method includes inserting hint instructions into an executable program code that demarcates single-use sections. A system includes a microprocessor to execute instructions in the default mode. The microprocessor detects a beginning and an ending of a single-use section that includes instructions that produce single-use vector register values.

公开(公告)号：US20210217220A1

公开(公告)日：2021-07-15

申请号：US16828926

申请日：2020-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anders M. KUGLER ,  Aayush ANKIT ,  Wilson Wai Lun FUNG

IPC: G06T15/04 ,  G06T15/50 ,  G06T1/60 ,  G06T1/20

Abstract: A texture filtering unit and a method are disclosed that provide multiple variants of an approximate trilinear filtering operation. A texture sampling and filtering unit may be configured to determine a level-of-detail (LOD) value for a sample point in texture space, and select, based on the LOD value, a fine mip-level and a coarse mip-level from the mip-map. The closer of the two selected mip-levels to the sample point is determined, and farther of the two selected mip-levels from the sample point is determined. A first quad of texels in the closer mip-level and a second quad of texels in the farther mip-level are then determined. A total of five or fewer texels are selected from the first quad of texels and from the second quad of texels. A filtered value for the sample point is determined based on an approximate trilinear filtering operation on the selected texels.

公开(公告)号：US20220300284A1

公开(公告)日：2022-09-22

申请号：US17471156

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Abhay Raj Kumar GUPTA ,  Wilson Wai Lun FUNG

IPC: G06F9/30 ,  G06F16/172 ,  G06T1/20

Abstract: A method for performing opportunistic write-back discard of single-use vector register values. The method includes executing instructions of a GPU in a default mode, detecting a beginning of a single-use section that includes instructions that produce single-use vector register values, and executing instructions in a single-use mode. The method includes discarding the write-back of a single-use vector register value if the single-use value gets forwarded either via a bypass path or via register file cache. The method includes inserting hint instructions into an executable program code that demarcates single-use sections. A system includes a microprocessor to execute instructions in the default mode. The microprocessor detects a beginning and an ending of a single-use section that includes instructions that produce single-use vector register values.

公开(公告)号：US20220083473A1

公开(公告)日：2022-03-17

申请号：US17175607

申请日：2021-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anshujit SHARMA ,  Sushant KONDGULI ,  Zhenhong LIU ,  Wilson Wai Lun FUNG ,  Arun RADHAKRISHNAN ,  Wayne YAMAMOTO

IPC: G06F12/0875 ,  G06F12/02 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.

公开(公告)号：US20200334037A1

公开(公告)日：2020-10-22

申请号：US16445199

申请日：2019-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wilson Wai Lun FUNG ,  Mrinal DEO

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/355

Abstract: According to one general aspect, an apparatus may include execution unit circuits, each configured to access one or more pieces of data. The apparatus may include local register file circuits, each associated with a respective execution unit circuit and each configured to store data. The apparatus may include a main register circuit. The main register circuit may include a main register file circuit configured to store data. The main register circuit may include a local index register circuit configured to map an index supplied by the main register file circuit to a storage location in the local register file circuits. The main register circuit may be configured to: receive from a control circuit a request to access the storage location of the specified data, and supply a target local register file circuit with the target local register file circuit's storage location of the specified data.