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公开(公告)号:US20180329823A1
公开(公告)日:2018-11-15
申请号:US15729068
申请日:2017-10-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Edward A. BREKELBAUM , Arun RADHAKRISHNAN
IPC: G06F12/0862 , G06N99/00 , G06F9/38 , G06F12/0811 , G06F12/0875 , G06F9/30
CPC classification number: G06F12/0862 , G06F3/06 , G06F9/30043 , G06F9/3802 , G06F12/0811 , G06F12/0875 , G06F2212/452 , G06F2212/6024 , G06F2212/62 , G06N20/00
Abstract: Apparatuses, systems, methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, an SMS prefetch engine uses trigger-to-trigger stride detection to promote training table entries to pattern history table (PHT) entries and to drive spatially related prefetches in more distant regions. In another aspect, an SMS prefetch engine maintains a blacklist of program counter (PC) values to not use as trigger values. In yet another aspect, an SMS prefetch engine uses hashed values of certain fields, such as the trigger PC, in entries of, e.g., filter tables, training tables, and PHTs, as index values for the table.
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公开(公告)号:US20150199275A1
公开(公告)日:2015-07-16
申请号:US14325343
申请日:2014-07-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Arun RADHAKRISHNAN , Kevin LEPAK , Rama GOPAL , Murali CHINNAKONDA , Karthik SUNDARAM , Brian GRAYSON
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F12/10 , G06F2212/6022
Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher, and a pre-fetch scheduler. The cache pre-fetcher may be configured to predict, based at least in part upon a virtual address, data to be retrieved from a memory system. The pre-fetch scheduler may be configured to convert the virtual address of the data to a physical address of the data, and request the data from one of a plurality of levels of the memory system. The memory system may include a plurality of levels, each level of the memory system configured to store data.
Abstract translation: 根据一个一般方面,设备可以包括高速缓存预取器和预取调度器。 高速缓存预取器可以被配置为至少部分地基于虚拟地址预测要从存储器系统检索的数据。 预取调度器可以被配置为将数据的虚拟地址转换为数据的物理地址,并且从存储器系统的多个级别之一请求数据。 存储器系统可以包括多个级别,存储器系统的每个级别被配置为存储数据。
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公开(公告)号:US20220067876A1
公开(公告)日:2022-03-03
申请号:US17146491
申请日:2021-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sushant KONDGULI , Arun RADHAKRISHNAN , Zachary D. NEYLAND , David C. TANNENBAUM
Abstract: A method of processing a workload in a graphics processing unit (GPU) may include detecting a work item of the workload in the GPU, determining a cache policy for the work item, and operating at least a portion of a cache memory hierarchy in the GPU for at least a portion of the work item based on the cache policy. The work item may be detected based on information received from an application and/or monitoring one or more performance counters by a driver and/or hardware detection logic. The method may further include monitoring one or more performance counters, wherein the cache policy for the work item may be determined and/or changed based on the one or more performance counters. The cache policy for the work item may be selected based on a runtime learning model.
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公开(公告)号:US20150199276A1
公开(公告)日:2015-07-16
申请号:US14451375
申请日:2014-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Arun RADHAKRISHNAN , Karthik SUNDARAM , Brian GRAYSON
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F2212/6026 , G06F2212/6028
Abstract: According to one general aspect, a method may include receiving, by a pre-fetch unit, a demand to access data stored at a memory address. The method may include determining if a first portion of the memory address matches a prior defined region of memory. The method may further include determining if a second portion of the memory address matches a previously detected pre-fetched address portion. The method may also include, if the first portion of the memory address matches the prior defined region of memory, and the second portion of the memory address matches the previously detected pre-fetched address portion, confirming that a pre-fetch pattern is associated with the memory address.
Abstract translation: 根据一个一般方面,一种方法可以包括通过预取单元接收访问存储在存储器地址中的数据的需求。 该方法可以包括确定存储器地址的第一部分是否匹配先前定义的存储器区域。 该方法还可以包括确定存储器地址的第二部分是否匹配先前检测到的预取地址部分。 该方法还可以包括,如果存储器地址的第一部分与存储器的先前定义的区域匹配,并且存储器地址的第二部分与先前检测到的预取地址部分匹配,则确认预取模式与 内存地址。
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公开(公告)号:US20220083473A1
公开(公告)日:2022-03-17
申请号:US17175607
申请日:2021-02-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Anshujit SHARMA , Sushant KONDGULI , Zhenhong LIU , Wilson Wai Lun FUNG , Arun RADHAKRISHNAN , Wayne YAMAMOTO
IPC: G06F12/0875 , G06F12/02 , G06T1/20 , G06T1/60
Abstract: A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.
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