公开(公告)号：US20230205711A1

公开(公告)日：2023-06-29

申请号：US18170949

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-joo JUNG ,  Jang-Woo LEE ,  Byung-hoon JEONG ,  Jeong-don IHM

IPC: G06F13/16 ,  G06F11/30 ,  G06F11/07 ,  G06F1/10 ,  G06F12/0882 ,  G06F18/214

CPC classification number: G06F13/1673 ,  G06F1/10 ,  G06F11/0757 ,  G06F11/3037 ,  G06F12/0882 ,  G06F18/2148

Abstract: A memory device includes a path state check circuit configured to check states of signal transmission paths, each signal transmission path including a data transmission path and a clock transmission path of the memory device. The path state check circuit includes a sampling circuit configured to perform a sampling operation by using pattern data that has passed through the data transmission path and a clock signal that has passed through the clock transmission path, and generate sample data, and a management circuit configured to generate a comparison of the sample data with the pattern data and manage check result information indicating whether a re-training operation for the memory device is to be performed, based on a result of the comparison.