公开(公告)号：US20210182223A1

公开(公告)日：2021-06-17

申请号：US17016883

申请日：2020-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hyun CHOI ,  Hyun-Joong KIM ,  Joon Sik SOHN ,  Woong-Jae SONG ,  Soo-Woong AHN ,  Seung-Hyun CHO

IPC: G06F13/16 ,  G11C7/10

Abstract: Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.

公开(公告)号：US20190259732A1

公开(公告)日：2019-08-22

申请号：US16115741

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Hwan CHOO ,  Woong-Jae SONG

IPC: H01L25/065 ,  H01L25/18 ,  G11C8/18 ,  G11C5/06 ,  G06F3/06

Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the first processor through the second channel.