公开(公告)号：US20230147901A1

公开(公告)日：2023-05-11

申请号：US17819330

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN YOUNG PARK ,  HYUK KIM ,  YEON GEUN YOOK ,  YOUNG SIK LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573

Abstract: Semiconductor memory devices may include a cell substrate including a cell array region, first and second extension regions and a through region, a first mold structure including first gate electrodes stacked in a stepwise manner, a first interlayer insulating layer extending conformally on the first gate electrodes on the second extension region, a second interlayer insulating layer on the first interlayer insulating layer, a second mold structure including second gate electrodes on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner, a channel structure in the first and second mold structures on the cell array region, a first cell contact structure in the first mold structure on the second extension region, and a second cell contact structure in the first and second mold structures on the first extension region. The first and second interlayer insulating layers may have different impurity concentrations.