公开(公告)号：US20220229668A1

公开(公告)日：2022-07-21

申请号：US17717302

申请日：2022-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung AHN ,  Wooseok CHANG ,  Yongha PARK

IPC: G06F9/38 ,  G06F9/48 ,  G06F13/12 ,  G06N3/08

Abstract: A method of operating an accelerator includes receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator, processing the received commands according to a subject of performance of each of the commands, and transmitting a completion message indicating that performance of the commands is completed to the CPU after the performance of the commands is completed.

公开(公告)号：US20240220252A1

公开(公告)日：2024-07-04

申请号：US18609501

申请日：2024-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha PARK

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F13/16

CPC classification number: G06F9/3004 ,  G06F9/3001 ,  G06F9/34 ,  G06F9/3877 ,  G06F13/1668

Abstract: An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation operation on sets of data stored in a memory and an aggregation operation on results processed by the processing core; and provide a result of the performing of the operation.

公开(公告)号：US20210191728A1

公开(公告)日：2021-06-24

申请号：US16922073

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyung AHN ,  Wooseok CHANG ,  Yongha PARK

IPC: G06F9/38 ,  G06F9/48 ,  G06N3/08 ,  G06F13/12

Abstract: A method of operating an accelerator includes receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator, processing the received commands according to a subject of performance of each of the commands, and transmitting a completion message indicating that performance of the commands is completed to the CPU after the performance of the commands is completed.

公开(公告)号：US20250166721A1

公开(公告)日：2025-05-22

申请号：US18761985

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha PARK ,  Seaeun Park ,  Saeeun Kim

IPC: G11C29/32 ,  G06F11/22

Abstract: A nonvolatile memory device includes at least one first universal interface bus (UIB) circuit coupled to a plurality of input/output (I/O) pads, at least one second UIB circuit coupled to the plurality of I/O pads, a core block including a first input terminal coupled to another block, and a plurality of second input terminals coupled to a first output terminal of the at least one first UIB circuit and a second output terminal of the at least one second UIB circuit, and at least one block configured to activate the at least one second UIB circuit.

公开(公告)号：US20200168271A1

公开(公告)日：2020-05-28

申请号：US16421855

申请日：2019-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ihor VASYLTSOV ,  Youngnam HWANG ,  Jinmin KIM ,  Yongha PARK ,  Hyunsik PARK ,  Jaewon YANG

IPC: G11C11/54 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G06N3/04

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

公开(公告)号：US20210192326A1

公开(公告)日：2021-06-24

申请号：US16922257

申请日：2020-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha PARK

IPC: G06N3/063 ,  G06F9/50 ,  G06F9/30 ,  G06F9/34 ,  G06F7/50

Abstract: An interconnect device may include one or more hardware-implemented modules configured to: receive a command from a processing core; perform, based on the received command, an operation including either one or both of an accumulation operation on sets of data stored in a memory and an aggregation operation on results processed by the processing core; and provide a result of the performing of the operation.

公开(公告)号：US20150221063A1

公开(公告)日：2015-08-06

申请号：US14539609

申请日：2014-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolkyoo KIM ,  Kilwhan LEE ,  Yongha PARK

IPC: G06T1/60 ,  G06F12/08

CPC classification number: G06T1/60 ,  G06F12/0862 ,  G06F2212/455 ,  G06F2212/6022 ,  Y02D10/13

Abstract: Provided are a multimedia data processing system and a selective caching method. The selective caching method in the multimedia data processing system includes inserting cacheability indicator information into an address translation table descriptor undergoing memory allocation to a graphics resource when the graphics resource needs to be cached and selectively controlling whether or not to prefetch multimedia data of the graphics resource present in a main memory to a system level cache memory, with reference to cacheability indicator information during an address translation operation of a graphic processing unit (GPU). The inventive concept can be implemented in a wide variety of computer-based systems having a graphical output, such as cell phones, laptops, tablets, and personal computers, as only a few examples.

Abstract translation: 提供了多媒体数据处理系统和选择性缓存方法。 多媒体数据处理系统中的选择性高速缓存方法包括：当图形资源需要被缓存并且选择性地控制是否预取图形资源的多媒体数据时，将高速缓存性指示符信息插入到对图形资源进行存储器分配的地址转换表描述符中 参考图形处理单元（GPU）的地址转换操作期间的可缓存性指示符信息，将主存储器存在于系统级缓存存储器中。 只有少数示例，本发明的概念可以在具有图形输出的各种基于计算机的系统中实现，例如手机，笔记本电脑，平板电脑和个人计算机。