公开(公告)号：US10062606B2

公开(公告)日：2018-08-28

申请号：US15837132

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkong Siew ,  Seongho Park

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266

Abstract: Methods of fabricating a semiconductor device include forming a lower interlayer insulating layer and a conductive base structure, and forming a middle interlayer insulating layer covering the lower interlayer insulating layer and the conductive base structure. The methods include etching the middle interlayer insulating layer to form a via hole and an interconnection trench vertically aligned with the via hole, and forming a via barrier layer on inner walls of the via hole and an interconnection barrier layer on inner walls and a bottom of the interconnection trench, the via barrier layer not being formed on an upper surface of the conductive base structure The methods include forming a via plug on the via barrier layer to fill the via hole, forming a seed layer on the interconnection trench and the via plug, forming an interconnection electrode on the seed layer, and forming an interconnection capping layer on the interconnection electrode.