公开(公告)号：US20250040282A1

公开(公告)日：2025-01-30

申请号：US18628099

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihun LIM ,  Sungki MIN ,  Chang Kyu LEE ,  Yongkun JO

IPC: H01L27/146

Abstract: An image sensor includes a substrate region having a photoelectric conversion region and a floating diffusion region therein. The floating diffusion region is configured to receive charges generated in the photoelectric conversion region in response to light incident the photoelectric conversion region. First and second horizontal conductive lines are provided that extend on the substrate region, but at different heights relative to a surface of the substrate region. The first horizontal conductive line is electrically connected to the floating diffusion region and has a thickness smaller than a thickness of the second horizontal conductive line. In addition, the first horizontal conductive line extends closer to the substrate region than the second horizontal conductive line.

公开(公告)号：US20250031476A1

公开(公告)日：2025-01-23

申请号：US18669876

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho JANG ,  Jonghyun GO ,  Doowon KWON ,  Changkyu LEE ,  Yongkun JO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/522 ,  H04N25/79

Abstract: An image sensor includes a first semiconductor chip including a first semiconductor substrate including a plurality of pixels and a first wiring structure having a first bonding pad; a second semiconductor chip including a second semiconductor substrate having pixel signal generator circuits, a second wiring structure on the second semiconductor substrate and having an upper bonding pad bonded to the first bonding pad, a back side insulating layer on a lower surface of the second semiconductor substrate and including a shielding metal pattern buried therein, and a conductive through-via penetrating the back side insulating layer and the first semiconductor substrate, and a third semiconductor chip including a bonding layer having a lower bonding pad connected to the conductive through via, a third semiconductor substrate including logic devices, and a third wiring structure having a third bonding pad bonded to the lower bonding pad.