公开(公告)号：US20240321911A1

公开(公告)日：2024-09-26

申请号：US18537644

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkwan KIM ,  Joonhyuk HWANG ,  Jonghyun GO ,  Changkyu LEE

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685

Abstract: An image sensor having a structure in which a light-blocking film having an excellent light-blocking effect is provided in a light-blocking region includes a first substrate including a first surface and a second surface, the first surface including a plurality of transistors, and the second surface being opposite to the first surface and configured to receive light, the first substrate comprising a pixel array region and a light-blocking region, an anti-reflection structure on the second surface of the first substrate in the pixel array region and the light-blocking region, and a light-blocking structure on the anti-reflection structure in the light-blocking region, wherein the light-blocking structure comprises a plurality of film that are sequentially stacked, the plurality of film including at least a first conductive film, a first insulating film, and a second conductive film.

公开(公告)号：US20250031476A1

公开(公告)日：2025-01-23

申请号：US18669876

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho JANG ,  Jonghyun GO ,  Doowon KWON ,  Changkyu LEE ,  Yongkun JO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/522 ,  H04N25/79

Abstract: An image sensor includes a first semiconductor chip including a first semiconductor substrate including a plurality of pixels and a first wiring structure having a first bonding pad; a second semiconductor chip including a second semiconductor substrate having pixel signal generator circuits, a second wiring structure on the second semiconductor substrate and having an upper bonding pad bonded to the first bonding pad, a back side insulating layer on a lower surface of the second semiconductor substrate and including a shielding metal pattern buried therein, and a conductive through-via penetrating the back side insulating layer and the first semiconductor substrate, and a third semiconductor chip including a bonding layer having a lower bonding pad connected to the conductive through via, a third semiconductor substrate including logic devices, and a third wiring structure having a third bonding pad bonded to the lower bonding pad.