公开(公告)号：US20210210431A1

公开(公告)日：2021-07-08

申请号：US17018400

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyoung KIM ,  Young-Jin KWON ,  Geun Won LIM

IPC: H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

公开(公告)号：US20210335811A1

公开(公告)日：2021-10-28

申请号：US17143216

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong CHUNG ,  Ho Jin KIM ,  Young-Jin KWON ,  Dong Seog EUN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  G11C8/14

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US20240088045A1

公开(公告)日：2024-03-14

申请号：US18514716

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyoung KIM ,  Young-Jin KWON ,  Geun Won LIM

IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

公开(公告)号：US20230328989A1

公开(公告)日：2023-10-12

申请号：US18209983

申请日：2023-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong CHUNG ,  Ho Jin KIM ,  Young-Jin KWON ,  Dong Seog EUN

IPC: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.