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    VERTICAL MEMORY DEVICE
    1.
    发明申请
    VERTICAL MEMORY DEVICE 审中-公开

    公开(公告)号：US20200058671A1

    公开(公告)日：2020-02-20

    申请号：US16270570

    申请日：2019-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Hyoung KIM ,  Kwang Soo KIM ,  Seok Cheon BAEK ,  Geun Won LIM

    IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573

    Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    3.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240088045A1

    公开(公告)日：2024-03-14

    申请号：US18514716

    申请日：2023-11-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung KIM ,  Young-Jin KWON ,  Geun Won LIM

    IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

    VERTICAL MEMORY DEVICE
    4.
    发明申请
    VERTICAL MEMORY DEVICE 有权

    公开(公告)号：US20220130851A1

    公开(公告)日：2022-04-28

    申请号：US17569497

    申请日：2022-01-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Hyoung KIM ,  Kwang Soo KIM ,  Seok Cheon BAEK ,  Geun Won LIM

    IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11548

    Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210210431A1

    公开(公告)日：2021-07-08

    申请号：US17018400

    申请日：2020-09-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung KIM ,  Young-Jin KWON ,  Geun Won LIM

    IPC: H01L23/535 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210280599A1

    公开(公告)日：2021-09-09

    申请号：US16998141

    申请日：2020-08-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Geun Won LIM

    IPC: H01L27/11582 ,  H01L27/11565

    Abstract: A nonvolatile memory device and a method of fabricating a nonvolatile memory device, the device including a substrate; a first mold structure on the substrate, the first mold structure including a plurality of first mold insulation films and a plurality of first gate electrodes, which are alternately stacked; a channel structure that penetrates the first mold structure and intersects the plurality of first gate electrodes; and at least one insulation filler that intersects the plurality of first mold insulation films and the plurality of the first gate electrodes, wherein the first mold structure is electrically separated by a word line cutting region extending in a first direction such that the first mold structure includes a first block region and a second block region, and the at least one insulation filler is in the word line cutting region and connects the first block region and the second block region.

    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210111186A1

    公开(公告)日：2021-04-15

    申请号：US16852907

    申请日：2020-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang Min KIM ,  Seung Min SONG ,  Jae Hoon SHIN ,  Joong Shik SHIN ,  Geun Won LIM

    IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/311

    Abstract: A nonvolatile memory device with improved product reliability and a method of fabricating the same is provided. The nonvolatile memory device comprises a substrate, a first mold structure disposed on the substrate and including a plurality of first gate electrodes, a second mold structure disposed on the first mold structure and including a plurality of second gate electrodes and a plurality of channel structures intersecting the first gate electrodes and the second gate electrodes by penetrating the first and second mold structures, wherein the first mold structure includes first and second stacks, which are spaced apart from each other, and the second mold structure includes a third stack, which is stacked on the first stack, a fourth stack, which is stacked on the second stack, and first connecting parts, which connect the third and fourth stacks.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200020716A1

    公开(公告)日：2020-01-16

    申请号：US16251337

    申请日：2019-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung KIM ,  Kwang Soo KIM ,  Geun Won LIM

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28

    Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

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