公开(公告)号：US20200302981A1

公开(公告)日：2020-09-24

申请号：US16946217

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun KIM ,  Si-hong KIM ,  Tae-young OH ,  Kyung-soo HA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20220059148A1

公开(公告)日：2022-02-24

申请号：US17518888

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun KIM ,  Si-hong KIM ,  Tae-young OH ,  Kyung-soo HA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.