公开(公告)号：US20200302981A1

公开(公告)日：2020-09-24

申请号：US16946217

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun KIM ,  Si-hong KIM ,  Tae-young OH ,  Kyung-soo HA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20170154668A1

公开(公告)日：2017-06-01

申请号：US15334082

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-soo HA

IPC: G11C11/4094 ,  G11C11/4096 ,  H03K19/00

CPC classification number: G11C11/4094 ,  G11C7/1057 ,  G11C7/12 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/021 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/20 ,  G11C29/24 ,  G11C29/46 ,  G11C2029/0409 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2207/2254 ,  H03K19/0005

Abstract: A memory device may include a calibration circuit configured to perform a calibration operation of generating a pull-up control code and a pull-down control code in a calibration mode, and in a stress applying mode, turn on at least one of each of first and second transistor units to apply stress, and an on-die termination (ODT)/off-chip driver (OCD) circuit, a resistance value of the ODT/OCD circuit being adjusted in response to at least one of the pull-up control code and the pull-down control code. The calibration circuit includes a pull-up control code generator including the first transistor unit and a pull-down control code generator including the second transistor unit.

公开(公告)号：US20190156872A1

公开(公告)日：2019-05-23

申请号：US16196777

申请日：2018-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun Kim ,  Si-hong KIM ,  Tae-young OH ,  Kyung-soo HA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/1093 ,  G11C8/10 ,  G11C8/18 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254 ,  G11C2207/2272

Abstract: There are provided, a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.

公开(公告)号：US20220059148A1

公开(公告)日：2022-02-24

申请号：US17518888

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-hun KIM ,  Si-hong KIM ,  Tae-young OH ,  Kyung-soo HA

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C8/10 ,  G11C29/50 ,  G11C29/02

Abstract: There are provided a memory device for supporting a command bus training (CBT) mode and a method of operating the same. The memory device is configured to enter a CBT mode or exit from the CBT mode in response to a logic level of a first data signal, which is not included in second data signals, which are in one-to-one correspondence with command/address signals, which are used to output a CBT pattern in the CBT mode. The memory device is further configured to change a reference voltage value in accordance with a second reference voltage setting code received by terminals associated with the second data signals, to terminate the command/address signals or a pair of data clock signals to a resistance value corresponding to an on-die termination (ODT) code setting stored in a mode register, and to turn off ODT of data signals in the CBT mode.