公开(公告)号：US20240186277A1

公开(公告)日：2024-06-06

申请号：US18481823

申请日：2023-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Chungsun Lee

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/17517 ,  H01L2224/26125 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/1434 ,  H01L2924/3511 ,  H10B80/00

Abstract: A semiconductor package includes a plurality of semiconductor chips that face each other, a plurality of bumps disposed on a front surface or a rear surface of one of the plurality of semiconductor chips, an underfill layer that surrounds the plurality of bumps, and a plurality of insulating frames spaced apart from each other on the front or rear surface of one of the plurality of semiconductor chips. The plurality of insulating frames overlap a plurality of corner regions of the one of the plurality of semiconductor chips in a direction in which the plurality of semiconductor chips face each other.

公开(公告)号：US20240055414A1

公开(公告)日：2024-02-15

申请号：US18299795

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Chungsun Lee

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/48227

Abstract: A semiconductor package includes a first redistribution wiring layer, a first semiconductor device on an upper surface of the first redistribution wiring layer, a first sealing member on the first semiconductor device, a second redistribution wiring layer on the first sealing member such that a peripheral region of a lower surface of the second redistribution wiring layer is free of the first sealing member, at least one second semiconductor device on an upper surface of the second redistribution wiring layer, and a plurality of bonding wirings electrically connecting first redistribution connection pads on a lower surface of the first redistribution wiring layer and second redistribution connection pads on the peripheral region of the lower surface of the second redistribution wiring layer.

公开(公告)号：US11289438B2

公开(公告)日：2022-03-29

申请号：US16985445

申请日：2020-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiseok Hong ,  Unbyoung Kang ,  Myungsung Kang ,  Taehun Kim ,  Sangcheon Park ,  Hyuekjae Lee ,  Jihwan Hwang

IPC: H01L29/40 ,  H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

公开(公告)号：US20220020713A1

公开(公告)日：2022-01-20

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L23/00 ,  H01L25/065

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

公开(公告)号：US12218086B2

公开(公告)日：2025-02-04

申请号：US17716054

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongbum Kwon ,  Unbyoung Kang

IPC: H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a semiconductor package includes bonding first the and second structures, such that a first bonding structure is directly bonded to a second bonding structure. The forming of the first structure includes; forming a blocking layer on a metallic material layer including a first portion covering a concaved portion of the metallic material layer and a second portion covering a non-concaved portion of the metallic material layer, performing a first planarization process to remove the second portion of the blocking layer while the first portion of the blocking layer remains, performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer, performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer.

公开(公告)号：US20240347510A1

公开(公告)日：2024-10-17

申请号：US18585468

申请日：2024-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongil Lee ,  Byeongchan Kim ,  Unbyoung Kang ,  Jumyong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03616 ,  H01L2224/05647 ,  H01L2224/13027 ,  H01L2224/81895 ,  H01L2225/06541 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a plurality of through electrodes, first bonding pads provided on a first surface of a first substrate, a first passivation layer provided on the first surface and exposing the first bonding pads, a polishing stop layer pattern provided on a second surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads provided on the polishing stop layer pattern. The second semiconductor chip includes third bonding pads provided on a first surface of a second substrate, and a second passivation layer provided on the first surface of the second substrate and exposing the third bonding pads. The first bonding pads and the third bonding pads are directly bonded to each other.

公开(公告)号：US20240321667A1

公开(公告)日：2024-09-26

申请号：US18387682

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seunghun Shin ,  Soyeon Kwon ,  Unbyoung Kang ,  Yeongkwon Ko

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/3185 ,  H01L21/568 ,  H01L21/78 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06131 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/13014 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0665

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface opposite to the first surface, a second semiconductor chip stacked on the first surface of the first semiconductor chip, and a molding layer contacting the first surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer includes a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.

公开(公告)号：US11587906B2

公开(公告)日：2023-02-21

申请号：US17168238

申请日：2021-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US11569145B2

公开(公告)日：2023-01-31

申请号：US17188332

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Juhyun Lyu ,  Unbyoung Kang ,  Chulwoo Kim ,  Jongho Lee

IPC: H01L23/36 ,  H01L23/40 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

公开(公告)号：US20210384096A1

公开(公告)日：2021-12-09

申请号：US17188332

申请日：2021-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Lee ,  Juhyun Lyu ,  Unbyoung Kang ,  Chulwoo Kim ,  Jongho Lee

IPC: H01L23/36 ,  H01L25/065 ,  H01L23/40

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.