公开(公告)号：US20220166427A1

公开(公告)日：2022-05-26

申请号：US17515607

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul HWANG ,  Youngo LEE

IPC: H03K17/687 ,  H03K3/356

Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

公开(公告)号：US20210320660A1

公开(公告)日：2021-10-14

申请号：US17222197

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngo LEE ,  Ahreum KIM

IPC: H03K19/00 ,  H03K3/012

Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.