公开(公告)号：US20230169013A1

公开(公告)日：2023-06-01

申请号：US17965700

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsuk Moon ,  Hyunwoo Kang ,  Jaegeun Park ,  Sangmuk Hwang

IPC: G06F12/1081 ,  G06F12/1045 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F12/1045 ,  G06F13/28 ,  G06F2212/652 ,  G06F2213/28

Abstract: An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

公开(公告)号：US20240320173A1

公开(公告)日：2024-09-26

申请号：US18610528

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsuk Moon ,  Jaegeun Park ,  Jiwon Chang ,  Sangmuk Hwang

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F2213/28

Abstract: A storage device includes a buffer memory, a first direct memory access (DMA) circuit configured to provide data from a host to the buffer memory or data stored in the buffer memory to the host and output a first virtual address, a second DMA circuit configured to provide data read from a non-volatile memory to the buffer memory or the data stored in the buffer memory to the non-volatile memory and output a second virtual address, an address translation circuit configured to translate the first or second virtual address into a physical address when the first or second virtual address is included in a reference range and skip the translation operation when the first or second virtual address is excluded in the reference range. A buffer controller is configured to access the buffer memory based on the physical address of the first or second virtual address that is excluded.

公开(公告)号：US12182033B2

公开(公告)日：2024-12-31

申请号：US17965700

申请日：2022-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsuk Moon ,  Hyunwoo Kang ,  Jaegeun Park ,  Sangmuk Hwang

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/1081 ,  G06F13/28

Abstract: An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

公开(公告)号：US11983436B2

公开(公告)日：2024-05-14

申请号：US17827841

申请日：2022-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngsuk Moon ,  Jaegeun Park ,  Jongin Lee ,  Sangmuk Hwang

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.