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    Address translation cache and system including the same
    2.
    发明授权
    Address translation cache and system including the same 有权

    公开(公告)号：US12182033B2

    公开(公告)日：2024-12-31

    申请号：US17965700

    申请日：2022-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngsuk Moon ,  Hyunwoo Kang ,  Jaegeun Park ,  Sangmuk Hwang

    IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/1081 ,  G06F13/28

    Abstract: An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

    Memory controller and memory system
    3.
    发明授权
    Memory controller and memory system 有权

    公开(公告)号：US11983436B2

    公开(公告)日：2024-05-14

    申请号：US17827841

    申请日：2022-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngsuk Moon ,  Jaegeun Park ,  Jongin Lee ,  Sangmuk Hwang

    IPC: G06F3/06

    CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A memory controller includes a buffer memory including memory banks, one or more host access units configured to perform an access to the buffer memory for a host, one or more memory access units configured to perform an access to the buffer memory for a memory device, and a processor configured to control an operation of the memory controller. The processor divides the memory banks into an external memory bank group for an external operation related to the host, and an internal memory bank group for an internal operation within a memory system. The host access units access the external memory bank group. The memory access units access the external memory bank group to perform the external operation, and access the internal memory bank group to perform the internal operation.

    STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF
    5.
    发明申请
    STORAGE CONTROLLER MANAGING COMPLETION TIMING, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20220283962A1

    公开(公告)日：2022-09-08

    申请号：US17751798

    申请日：2022-05-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangmuk HWANG ,  Jaegeun Park ,  Hojun Shim ,  Byungchul Yoo

    IPC: G06F13/16 ,  G06F13/28

    Abstract: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

    Nonvolatile memory device and program method thereof
    7.
    发明授权
    Nonvolatile memory device and program method thereof 有权

    公开(公告)号：US09799402B2

    公开(公告)日：2017-10-24

    申请号：US15083834

    申请日：2016-03-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinwoo Kim ,  Seong Yeon Kim ,  Jaegeun Park ,  Hyo-Deok Shin ,  Younggeun Lee ,  Youngjin Cho

    IPC: G11C16/10 ,  G11C7/10

    CPC classification number: G11C16/10 ,  G11C7/1063

    Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

    ADDRESS TRANSLATION CACHE AND SYSTEM INCLUDING THE SAME
    8.
    发明公开
    ADDRESS TRANSLATION CACHE AND SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230169013A1

    公开(公告)日：2023-06-01

    申请号：US17965700

    申请日：2022-10-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngsuk Moon ,  Hyunwoo Kang ,  Jaegeun Park ,  Sangmuk Hwang

    IPC: G06F12/1081 ,  G06F12/1045 ,  G06F13/28

    CPC classification number: G06F12/1081 ,  G06F12/1045 ,  G06F13/28 ,  G06F2212/652 ,  G06F2213/28

    Abstract: An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

    Storage controller managing completion timing, and operating method thereof
    9.
    发明授权
    Storage controller managing completion timing, and operating method thereof 有权

    公开(公告)号：US11366770B2

    公开(公告)日：2022-06-21

    申请号：US16983471

    申请日：2020-08-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sangmuk Hwang ,  Jaegeun Park ,  Hojun Shim ,  Byungchul Yoo

    IPC: G06F13/16 ,  G06F13/28

    Abstract: A method of operating a storage controller that communicates with a host including a submission queue and a completion queue is provided. The operating method includes receiving a submission queue doorbell from the host, fetching a first command including a latency from the submission queue of the host in response to the received submission queue doorbell, processing the fetched first command, and writing a first completion, which indicates that the first command is completely processed, into the completion queue of the host at a timing based on the latency.

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